About the job
Become a part of Solidigm’s innovative Design Engineering Team as a 3D NAND IP Logic Design Engineer and contribute to the advancement of memory technology.
Key responsibilities include:
- Designing and verifying logic and circuit blocks for cutting-edge 3D NAND flash memory components.
- Defining micro-architecture specifications, implementing RTL in SystemVerilog, generating synthesis netlists with defined constraints, and performing static timing analysis to ensure design integrity.
- Developing and optimizing microcode-based algorithms (read, program, erase, power-on) for 3D NAND using proprietary instruction sets and compilers.
- Participating in the development of next-generation 3D NAND architecture to enhance density, die size, performance, power consumption, and cost efficiency.
- Working closely with pre-silicon verification teams to create unit-level test benches, implement SystemVerilog Assertions (SVAs), and execute full-chip RTL and gate-level simulation regressions to ensure robust coverage for various features.
- Reviewing pre-silicon analog and mixed-signal (AMS) simulations alongside post-silicon microprobe waveforms to conduct power and performance modeling.
- Collaborating with product engineering and technology development teams to define Read-Window-Budget (RWB) features and establish Design for Testability (DFT) methods aimed at reducing test time and cost while enhancing quality.
- Providing support for post-silicon debug and failure analysis across various configurations.
