About the job
Become part of Solidigm’s innovative Design Engineering Team as a 3D NAND IP Logic Design Engineer and play a pivotal role in advancing the future of memory technology.
Key Responsibilities:
- Architect, design, and validate logic and circuit blocks for cutting-edge 3D NAND flash memory components.
- Define micro-architecture specifications, implement RTL using SystemVerilog, generate synthesis netlists with relevant constraints, conduct static timing analysis, address timing violations, implement Engineering Change Orders (ECOs), and facilitate design sign-off.
- Develop and optimize microcode-based algorithms for 3D NAND operations (read, program, erase, power-on) utilizing proprietary instruction sets and compilers.
- Contribute to next-generation 3D NAND architecture enhancements and pathfinding aimed at improving density, die size, performance, power consumption, and cost efficiency.
- Collaborate with pre-silicon verification teams to create unit-level test benches, implement SystemVerilog Assertions (SVAs), execute full-chip RTL and gate-level simulation (GLS) regressions, and ensure functional and code coverage for various read-window-budget and customer-specific features.
- Analyze pre-silicon analog and mixed-signal (AMS) simulations and post-silicon microprobe waveforms to perform power and performance modeling, ensuring the functionality of both digital and analog blocks.
- Work in partnership with product engineering and technology development teams to define Read-Window-Budget (RWB) features and devise Design for Testability (DFT) methods that minimize testing time and costs while enhancing quality.
- Assist in post-silicon debugging and failure analysis across various configurations.

