Senior RTL Design Engineer – Silicon Engineering

Responsibilities:Assess architectural trade-offs concerning features, performance parameters, and system constraints. Define micro-architecture, implement RTL in Verilog/System Verilog, integrate it into the top level, and deliver a fully verified, synthesis/timing clean design. Collaborate closely with the verification team to ensure comprehensive design coverage and validation. Provide timing constraints for IPs and assist the physical implementation team with synthesis, timing closure, and formal checks. Engage in silicon bring-up and validation processes. Basic Qualifications:Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science. A minimum of 5 years of experience in RTL implementation. Preferred Skills and Experience:Adept at tackling complex challenges, especially those involving clock domain crossings and optimization.