Senior Digital/Mixed-Signal IC Design Engineer

QualificationsBachelor's degree in Electrical Engineering or related field with a minimum of 4 years of experience in high-performance digital or mixed-signal IC development using advanced CMOS processes. Proficient in Verilog RTL coding, including the design of state machines, adders, multipliers, and combinatorial logic. Strong grasp of digital design principles for mixed-signal control loops and the ability to design Verilog code for analog circuit control (e.g., digital backend for ADC, digital PLL). Familiarity with behavioral Verilog code, including wreals. Ability to develop comprehensive testbenches. Preferred experience with synthesis tools and a basic understanding of SystemVerilog and assertions. Familiarity with place-and-route tool flows is advantageous but not required. Basic knowledge of signal processing is preferred, MATLAB experience is a plus. Extensive experience with synthesis and place-and-route flows at the nano-meter scale. In-depth understanding of constraints in mixed-signal designs, including multiple clock domains and clock gating. Familiarity with timing closure and static timing analysis tools. Experience with scan chain vector generation and verification. Preference for experience with Cadence Encounter tool flow.