About the job
About Our Team
The Hardware team at OpenAI specializes in crafting custom silicon that fuels the most advanced AI systems globally. Our collaborative approach integrates system-level architecture with custom circuit designs, working closely with model and infrastructure teams to achieve remarkable breakthroughs in performance, power consumption, and efficiency across all layers of the technology stack.
About the Position
We are on the lookout for a talented Silicon Implementation Engineer with extensive knowledge in physical design and methodologies. As an integral part of our physical design team, you will play a crucial role in creating optimized datapath and interconnect solutions that enhance power, performance, and area (PPA) for cutting-edge AI accelerators.
In this role, you will collaborate closely with RTL designers to establish and implement effective physical design strategies. You will be responsible for developing innovative tools, processes, and methodologies that boost team productivity. Your contributions will significantly influence silicon performance, cost efficiency, and the overall quality and speed of our team’s output.
Key Responsibilities:
Design, develop, and manage tools, processes, and methodologies for physical implementation
Oversee the physical implementation of floorplan blocks from initial floorplanning to final signoff
Work in tandem with RTL designers to identify and implement optimal block solutions
Evaluate and enhance designs for timing, power, and area trade-offs, in collaboration with EDA vendors and ASIC partners
Required Qualifications:
Bachelor's degree with 4+ years, Master's with 2+ years, or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
Proven track record of successfully taping out complex silicon designs
Hands-on experience with block-level physical implementation and PPA optimization
Proficient in coding with Python, Bazel, and TCL
Solid experience in developing physical design tools, processes, and methodologies
Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification, and timing closure
In-depth knowledge of industry-standard tools and processes for physical synthesis, PNR, LEC, and power estimation
Preferred Qualifications:
Experience with AI or HPC-focused chips
Expertise in optimizing PPA for high-performance applications
