Software Engineering Intern - Simulation and Modeling

Join d-Matrix, where we are dedicated to harnessing the capabilities of generative AI to revolutionize technology. As pioneers in software and hardware innovation, we are constantly pushing the limits of what is achievable. Our workplace fosters a culture of respect and collaboration.We believe in humility and value direct communication. Our inclusive team thrives on diverse perspectives, which leads to innovative solutions. We are on the lookout for individuals who are passionate about solving problems and are driven to execute their ideas. Ready to explore your potential? Together, we can shape the limitless possibilities of AI.Location:This is a hybrid position, requiring you to work onsite at our Santa Clara office three days a week.12 Week Program: June 1st - August 21st or June 22nd - September 11thRole Overview: Runtime Engineer InternResponsibilities:We are seeking an enthusiastic intern with a background in Electrical Engineering (EE) or Computer Science (CS) to engage in embedded systems development, Linux software, RTOS, and security-related projects. Opportunities range from Linux software implementation to low-level embedded development on the RISC-V platform. Our projects encompass a complex multi-chip hardware architecture featuring PCIe 5.0, showcasing cutting-edge design. This role is perfect for individuals passionate about embedded technologies, whether through academic studies or personal projects. We are excited to offer training and mentorship to support your growth. The ideal candidate will have a solid foundation and a proactive approach to learning and thriving in a fast-paced, hands-on environment.

Join d-Matrix as we harness the power of generative AI to revolutionize technology. Positioned at the cutting edge of software and hardware innovation, we are committed to exploring the limits of what technology can achieve. Our culture thrives on respect and collaboration, where humility and open communication are paramount.We embrace inclusivity, leveraging diverse perspectives to forge superior solutions. We invite individuals who are passionate about overcoming challenges and are driven by results to join our team. Are you ready to discover your playground? Together, we can shape the limitless possibilities of AI.Location: Hybrid work model, with 3 days per week on-site at our headquarters in Santa Clara, CA.Role Overview:As a Senior Runtime Systems Engineer at d-Matrix, you will be pivotal in developing our AI compute platform, which focuses on in-memory computing for AI inference in datacenters. This role involves Runtime Software Engineering, where you will architect, develop, and validate the functionality and efficiency of firmware/software executed on multiprocessor system-on-chip (SoC), low-level drivers, and systems software that supports this SoC.You will take the lead on runtime performance aspects of our silicon products, architecting, documenting, and developing the runtime firmware for various on-chip multi-core CPU subsystems. Additionally, you will manage the delivery schedule and ensure compliance with d-Matrix coding and methodology guidelines, collaborating closely with the hardware team, hardware verification team, and other software team members.Key Responsibilities:Design and implement systems software for AI inference infrastructure.Identify, analyze, architect, develop, and debug systems software.Demonstrate experience in distributed and scale-out applications.Deliver high-quality code and debug complex problems effectively.

At d-Matrix, we are dedicated to unlocking the transformative power of generative AI technology. Positioned at the cutting edge of both software and hardware innovation, we continually strive to expand the boundaries of what technology can achieve. Our vibrant workplace culture emphasizes respect and collaboration.We believe in the values of humility and direct communication, fostering an inclusive team environment. Our diverse perspectives lead to innovative solutions. We are looking for passionate individuals who thrive on challenges and are motivated by tangible results. Are you ready to explore your potential? Together, we can shape the limitless possibilities of AI.LocationThis role is hybrid, requiring onsite work at our headquarters in Santa Clara, CA, for three days each week.12-Week Internship Program: June 1st - August 21st or June 22nd - September 11thRole OverviewAs a Machine Learning Research Intern, you will be part of our dynamic Machine Learning Team, focusing on exploring algorithm-hardware co-design research paths within d-Matrix's comprehensive solutions. You'll collaborate with a group of exceptional professionals dedicated to researching and developing cutting-edge deep learning techniques that are optimized for d-Matrix's AI compute engine. Additionally, you will have the chance to work alongside leading academic institutions, assisting customers in optimizing and deploying their workloads for practical AI applications on our platforms.Your Responsibilities:Design, implement, and assess efficient deep neural network architectures and algorithms tailored for d-Matrix's AI compute engine.Collaborate with both internal and external ML researchers to achieve R&D objectives.Work closely with the Software team to fulfill stack development milestones.Conduct research that informs hardware design decisions.Develop and maintain tools for high-level simulation and research purposes.Port and optimize customer workloads for deployment, create reference implementations, and evaluate their performance.Provide timely and effective progress reports and presentations.Contribute to the publication of research papers and intellectual property.Qualifications:Currently pursuing a Master's or PhD in Computer Science, Electrical and Computer Engineering, or a related scientific field.Strong foundation in machine learning algorithms and deep learning frameworks.Experience with programming languages such as Python or C++.Excellent communication skills, both verbal and written.Ability to work effectively in a collaborative team environment.

At d-Matrix, we are dedicated to unlocking the potential of generative AI and driving the evolution of technology. Positioned at the cutting edge of software and hardware innovation, we constantly challenge the limits of what can be achieved. Our corporate culture revolves around respect and collaboration, where humility and open communication are highly valued.We foster an inclusive team environment where diverse perspectives lead to superior solutions. We are on the lookout for passionate individuals eager to tackle challenges and who excel in execution. Are you ready to discover your playground? Together, we can shape the infinite possibilities of AI.Location:Santa Clara, CA headquarters or any of our regional offices. Remote work is an option.The Role: Staff Software Engineer - SIMD KernelsWhat You Will Do:As part of the SIMD Kernels team, you will contribute to the development of the software stack for our AI compute engine. Your responsibilities will include creating, enhancing, and maintaining software kernels for machine learning operators—such as softmax, layer normalization, and activation functions—for our next-generation AI hardware. You will also develop solutions that enhance our SDK, making it user-friendly for developers and facilitating performance analysis.You should possess experience in constructing software kernels for modern hardware architectures and understand how to effectively map algorithms and AI-framework computational graphs to those architectures. Your expertise will enable you to navigate hardware-software co-design trade-offs and deliver high-quality software efficiently in a fast-paced development environment.What You Will Bring:Minimum Requirements:MS or PhD in Computer Engineering, Mathematics, Physics, or a related discipline with 5+ years of industry experience.Strong understanding of computer architecture, data structures, system software, and machine learning principles.Proficiency in C/C++ and Python development within a Linux environment, utilizing standard development tools.Experience in implementing algorithms using C/C++ and Python.Familiarity with specialized hardware such as FPGAs, DSPs, GPUs, and AI accelerators, utilizing libraries like CUDA.Experience in implementing operators frequently employed in ML workloads—GEMMs, Convolutions, softmax, layer normalization, pooling, etc.Self-motivated team player with a robust ability to collaborate and innovate.

d-Matrix focuses on generative AI, combining software and hardware innovation to push technology forward. The team values respect, collaboration, and open communication, creating a workplace where different perspectives are welcomed. Interns join an inclusive group that believes diversity leads to better solutions. The company seeks individuals who enjoy tackling challenges and want to make a real impact through their work. Role overview The Applied AI Engineering Intern will work on projects related to Intelligent Manufacturing Systems. This role centers on applying AI concepts to practical engineering problems in manufacturing. What you will do Contribute to AI-driven solutions for manufacturing systems Collaborate with team members from diverse backgrounds Engage in problem-solving and execution-focused tasks Requirements Interest in AI and engineering Commitment to teamwork and open communication Motivation to learn and contribute to innovative projects

Role overview The Senior PCB Design Engineer at d-matrix in Santa Clara will take ownership of advanced printed circuit board design and development. This position combines technical leadership with hands-on design, supporting technology-driven products from concept to production. Responsibilities Lead PCB design projects from initial concept through production release Partner with engineering, manufacturing, and other teams to deliver high-quality, high-performance board designs Use current design tools and industry methodologies to enhance efficiency and board functionality Ensure all designs comply with company and industry standards for quality and reliability Collaboration This role requires frequent coordination with cross-functional teams to align on requirements, address technical challenges, and support the transition of designs into manufacturing.

Join d-Matrix, a pioneering company dedicated to harnessing the power of generative AI to revolutionize technology. Our commitment to innovation in software and hardware drives us to explore new frontiers. We foster a culture of respect and collaboration, where every team member’s voice is valued.At d-Matrix, we prioritize humility and open communication. Our inclusive team thrives on diverse perspectives, which lead to superior solutions. If you are passionate about overcoming challenges and driven by results, we invite you to explore the limitless potential of AI with us.Location:This role operates in a hybrid model, requiring you to work onsite at our Santa Clara, CA headquarters 3-5 days a week.Position Overview: Thermal Engineer - ContractYour Responsibilities:As a Thermal Engineer, you will play a crucial role in developing and supporting advanced liquid-cooled and air-cooled AI Inference solutions tailored for enterprise and high-performance computing (HPC) environments. Your tasks will encompass thermal architecture, design, analysis, and validation of thermal technologies within AI Accelerator Card and Server products. You will advocate for a design process that effectively integrates thermal solutions with server and rack systems for new product architectures. The ideal candidate will possess a robust foundational knowledge in implementing thermal solutions and designing cards, servers, and chassis/racks for enterprise electronics.Collaborate with design, testing, and engineering teams to develop and integrate innovative thermal solutions.Lead the design, deployment, and delivery of liquid-cooled and air-cooled HPC and AI supercomputing projects, ensuring alignment with performance, quality, and timeline goals. This includes evaluating system layout, power consumption, airflow, acoustics, sensors, and related mechanical requirements, as well as performing thermal and mechanical design for cooling systems at component, system, and rack levels.Oversee data center projects from inception to completion, ensuring high levels of customer satisfaction.Understand system design requirements for High-Performance Computing and AI workloads to create platform configuration guides for x86 and ARM servers.Prepare product drawings, BOM, SOP, DFM, and system design/test reports.Conduct thermal and mechanical debugging, system optimization, and documentation.

At d-Matrix, we are dedicated to unlocking the transformative power of generative AI in technology. As pioneers in software and hardware innovation, we continually redefine what is possible. Our work culture fosters respect and collaboration.We embrace humility and value open communication. Our inclusive team thrives on diverse perspectives that lead to superior solutions. We are on the lookout for individuals who are not only passionate about overcoming challenges but are also execution-oriented. Are you ready to explore your potential? Together, we can shape the limitless possibilities of AI.Location:Our headquarters is in Santa Clara, CA, but we welcome candidates from other locations within the US and Canada.The Role: Software Engineer, Developer and Qualification ToolsWhat You Will Do:Join our team responsible for creating developer and diagnostic tools for d-Matrix's state-of-the-art AI inference accelerators. You will be tasked with the design, development, enhancement, and maintenance of essential tools such as debuggers and profilers, along with hardware diagnostic tools for our cutting-edge hardware and software stack.

At d-Matrix, we are dedicated to unlocking the full potential of generative AI to drive technological transformation. Our team stands at the cutting edge of software and hardware innovation, continually pushing the limits of what is achievable. We foster a culture of respect and collaboration.We value humility and advocate for open communication. Our inclusive team embraces diverse perspectives, leading to superior solutions. We are looking for passionate individuals who thrive on challenges and are committed to execution. Are you ready to discover your playground? Together, we can shape the limitless possibilities of AI.Location:This position is hybrid, requiring you to work onsite at our Santa Clara office for 3 days a week. The internship runs for 12 weeks, either from June 1st to August 21st or from June 22nd to September 11th.Job Title: HW Design Verification InternWhat You Will DoYou will collaborate with a team to develop state-of-the-art LLM inference SoCs, gaining valuable hands-on experience with modern computing units, crossbars, chiplet interconnects, and high-performance memory interfaces.In this role, you will:Contribute to the functional verification of complex hardware blocks using UVM-based methodologies,Enhance bug detection through formal verification techniques utilizing SystemVerilog Assertions (SVA),Develop and maintain tools to boost simulation efficiency and verification productivity, andInvestigate how emerging AI-assisted workflows can strengthen DV methodologies.What You Will BringCurrently pursuing a Master’s or PhD in Electrical and Computer Engineering or a related field.Relevant coursework in Computer Architecture, Verilog, and/or FPGA development.Proficiency in SystemVerilog programming (required).Familiarity with SystemVerilog Assertions (SVA) is preferred but not mandatory.Current knowledge of AI SoC and/or LLM inference architectures is a plus.Strong verbal and written communication skills.

d-matrix seeks a Principal System Power Engineer based in Santa Clara. This position centers on creating and refining power systems that enable advanced technology products. Key responsibilities Design and enhance power systems for both new developments and established products Collaborate with engineering teams to deliver solutions that prioritize reliability and efficiency Apply specialized knowledge to projects that move the company’s technology forward Teamwork Work alongside engineers from various fields to address technical challenges and help deliver high-performance systems.

At d-Matrix, we are dedicated to unlocking the transformative potential of generative AI to redefine technology. Positioned at the leading edge of software and hardware innovation, we continually challenge the limits of possibility. Our workplace culture emphasizes respect and collaboration.We foster humility and value direct communication, creating an inclusive team where diverse perspectives lead to superior solutions. We invite individuals who are enthusiastic about overcoming challenges and who possess a strong execution drive. Are you ready to join us and explore the exciting realms of AI? Together, we can shape the infinite possibilities of this technology.Position Overview:As a Principal Software ML Test Engineer, you will lead junior team members in test planning, automation, and execution to productize the d-Matrix AI compute engine. You will contribute to the Software Qualification team, responsible for developing test suites, test cases, and testing infrastructure. Collaborating closely with software development teams, you will design, automate, and execute software and system use cases relevant to our next-gen AI chip software stack. Your role will involve implementing Python programs to test workloads and ML models within the Pytest framework, enhancing our end-to-end test suite and regression test suite in a CI/CD environment utilizing Jenkins and GitLab. You will work alongside the product, software development, and systems teams to ensure effective test coverage and results. Engaging fully in test case implementation, bug triaging, and debugging, you should be adept in advanced Python programming, capable of developing data structures and algorithms for testing purposes.

At d-Matrix, we are dedicated to unlocking the full potential of generative AI to revolutionize technology. Our company stands at the cutting edge of both software and hardware innovation, continuously expanding the limits of what is achievable. We foster a culture of collaboration and mutual respect.We hold humility in high regard and prioritize open communication. Our inclusive team thrives on diverse perspectives, driving us toward superior solutions. We are on the lookout for passionate individuals eager to face challenges and committed to execution. Are you ready to discover your playground? Together, we can explore the boundless opportunities of AI.Location:This position is Hybrid, requiring in-office attendance at our Santa Clara, CA headquarters 3-5 days per week.The Role: Staff Software Engineer - KernelsYour Responsibilities:As a key member of the team, you will contribute to the productization of the software stack for our AI compute engine. You will take charge of developing, enhancing, and maintaining software kernels for next-generation AI hardware. Your expertise in building software kernels for hardware architectures is essential. A robust understanding of various hardware architectures and the ability to map algorithms effectively is required. You will also need to translate computational graphs generated by AI frameworks into the underlying architecture. Your experience spans all facets of the full-stack toolchain, allowing you to navigate the intricacies of optimizing and balancing hardware-software co-design. You'll deliver scalable software solutions within tight development timelines, collaborating closely with compiler specialists and engaging with both software (ML, systems) and hardware (mixed signal, DSP, CPU) experts within the company.Your Qualifications:Minimum:MS in Computer Engineering, Mathematics, Physics, or a related field with 5+ years of industry experience; or a PhD in a related discipline with at least 1 year of experience.Thorough understanding of computer architecture, data structures, system software, and foundational machine learning concepts.Proficiency in C/C++ and Python development within Linux environments, utilizing standard development tools.Experience in algorithm implementation using high-level languages such as C/C++ and Python.

At d-Matrix, our mission is to unlock the transformative power of generative AI, driving the evolution of technology. We stand at the cutting edge of both software and hardware innovations, continually expanding the horizons of what is achievable. Our workplace culture is characterized by respect and collaboration.We place a high value on humility and encourage open communication. Our team is diverse, with a variety of perspectives that lead to superior solutions. We are on the lookout for individuals who are excited about overcoming challenges and are committed to delivering results. Are you ready to explore your potential? Together, we can shape the limitless possibilities of AI.Job Location:This is a hybrid role that requires you to work on-site at our Santa Clara, CA headquarters 3-5 days a week.About the Role:As a Principal Hardware Design Engineer at d-Matrix, you will play a pivotal role in our hardware organization, spearheading the development of cutting-edge platforms for our silicon-integrated AI accelerators. Your work will not merely involve designing boards; you will be laying down the physical framework that enables our Chiplet-based NPU (Neural Processing Unit) to tackle the most significant challenges in LLM inference within the industry.Key Responsibilities:Architectural Leadership: Oversee the complete hardware development lifecycle for sophisticated, high-performance AI accelerator PCIe cards and chassis platforms.Detailed Electrical Design: Manage schematic capture, component selection, and comprehensive BOM oversight for multi-rail, high-power designs.High-Speed Design: Design and supervise the layout of ultra-high-speed interfaces, such as PCIe Gen5/6, CXL, and custom chiplet-to-chiplet interconnects.Power Delivery (PDN): Develop resilient power delivery networks capable of managing high-current transients and low-voltage rails typical of advanced AI silicon.Cross-Functional Collaboration: Work closely with Silicon, Signal Integrity (SI/PI), Thermal, and Mechanical teams to ensure seamless product integration and performance.DFx & Manufacturing: Champion Design for Excellence (DFM, DFT, DFA) to guarantee high-yield production and long-term reliability in data center settings.Mentorship: Serve as a technical mentor, guiding junior engineers and establishing the standard for best practices in hardware design throughout the organization.

At d-Matrix, we are dedicated to harnessing the power of generative AI to revolutionize technology. Positioned at the cutting edge of software and hardware innovation, we continuously push the limits of what is achievable. Our workplace culture is defined by mutual respect and collaboration.We hold humility in high regard and prioritize open communication. Our team is diverse and inclusive, with varied perspectives fostering enhanced solutions. We are on the lookout for individuals who are passionate about overcoming challenges and are motivated by results. Are you ready to explore your potential? Together, we can mold the infinite possibilities of AI.Location:This position is hybrid, requiring onsite work at our Santa Clara, CA headquarters three days a week.Key Responsibilities:d-Matrix seeks a Hardware Platform Engineering leader to design and develop state-of-the-art products centered around our inference accelerators. You will collaborate with key customers, internal teams, and other vital stakeholders to drive robust system solutions. This role involves analyzing technical requirements, defining usage scenarios, and utilizing a broad range of technologies to deliver AI server and rack-scale solutions that provide exceptional customer experiences with d-Matrix inference accelerators.Collaborate closely with data center customers and OEM/ODM partners to facilitate the design, development, and qualification of servers, racks, and clusters using d-Matrix accelerators.Engage with team members across engineering, product, customer relations, and OEM/SI partners to validate, qualify, and enhance server, rack, and cluster solutions.Contribute to future product generations by providing insights on system architecture and technology through early engagement with customers and industry partners.

Join d-Matrix, where we are dedicated to leveraging the power of generative AI to revolutionize technology. We are pioneering in both software and hardware innovation, constantly expanding the limits of what is achievable. Our workplace culture emphasizes respect and collaboration.We greatly value humility and encourage open communication. Our team is diverse and inclusive, where varied perspectives contribute to superior solutions. We seek individuals who are passionate about overcoming challenges and are motivated by results. Are you ready to discover your potential? Together, we can explore the vast possibilities of AI.Location:This position is hybrid, requiring onsite work at our headquarters in Santa Clara, CA for three days each week.Role Overview: Senior Staff Design Verification EngineerKey Responsibilities:We aim to build a company culture that withstands the tests of time. This role presents a unique opportunity for you to express your creativity and emerge as a leader in an industry poised to make a global impact. We are committed to fostering a culture of transparency, inclusiveness, and intellectual honesty, ensuring that all team members continuously learn and enjoy the journey. You will work on pioneering our industry’s first highly programmable in-memory computing architecture, applicable across a wide range of applications from cloud to edge. Collaborate with a highly experienced team dedicated to building a successful business.Qualifications:Minimum qualifications include:A Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 12+ years of industry experience, or a Master's degree in Electrical Engineering, Computer Science, or a related field with 7+ years of experience.Proven experience throughout the SoC verification cycle from architecture to tape-out and bring-up.Strong understanding of verification methodologies such as UVM/OVM.Hands-on experience with ASIC-SoC design verification testing and debugging.Proficiency in SystemVerilog randomization constraints, coverage, and assertion methodologies.Excellent problem-solving skills and a fervent enthusiasm for tackling challenges, particularly within the AI domain.Extensive experience with SystemVerilog and verification methodologies (UVM/OVM/VMM).

Join the innovative team at d-Matrix, where we are dedicated to harnessing the power of generative AI to revolutionize technology. We are pioneers in software and hardware advancements, constantly pushing the envelope of what is feasible. Our workplace is built on a foundation of respect and collaboration.We value humility and prioritize open communication. Our inclusive team thrives on diverse perspectives, leading to superior solutions. If you're passionate about overcoming challenges and driven by results, we invite you to explore your playground with us. Together, let's unlock the endless possibilities of AI.Location: This role requires you to work onsite at our Santa Clara, CA headquarters three days a week.What You Will Do:Prepare for an exciting adventure as you engage in the bring-up, validation, and debugging of a revolutionary interference accelerator chip/chiplets! Anticipate the following responsibilities:· Lead the bring-up, validation, and debugging of cutting-edge interference accelerator chiplets, including the validation of high-speed serial protocols such as PCIe Gen5, high-speed memory interfaces like LPDDR5, and die-to-die chiplet interconnect blocks.· Innovate and implement:** Collaborate with your energetic team to develop and execute detailed test bring-up and validation plans, alongside automating randomization of software/firmware kernel functions and logging instrumentation with self-checking post processors.· Create impactful test scripts:** Design test scripts and embedded firmware functions for host systems to validate critical aspects of our high-speed interfaces, including PCIe, LPDDR, and D2D, expanding the frontiers of technology.· Equip your environment:** Work with your team to procure state-of-the-art lab equipment, ensuring you have the necessary tools for success.· Collaborate effectively:** Partner closely with hardware, software, and operations teams to tackle exciting challenges such as ATE tests and hardware/software debugging, nurturing a culture of teamwork and innovation.

Join d-Matrix, where we are dedicated to harnessing the power of generative AI to revolutionize technology. As pioneers in software and hardware innovation, we continuously expand the limits of what is achievable. Our organizational culture promotes respect and collaboration, fostering an environment where everyone’s contributions are valued.We uphold humility and encourage open communication. Our inclusive team thrives on diverse perspectives, leading to superior solutions. We invite individuals who are passionate about overcoming challenges and are results-driven. Are you ready to explore your potential? Together, we can unlock the infinite possibilities of AI.Location: Hybrid (Santa Clara, CA) or RemoteRole Overview: Principal AI Security Architectd-Matrix is on the lookout for an exceptional security architect to integrate robust secure computing principles into our high-performance AI accelerator systems, designed to meet or exceed the needs of our datacenter clients. Adopting a holistic approach to security, we embed security features across the entire stack—from silicon to application level—to ensure that our customers' workloads operate in a reliable and secure environment, regardless of deployment scale.Key Responsibilities:Contribute to the design of hardware and software security features that will enhance our next-generation inference accelerators.Stay updated on the latest research in machine learning, architecture, and security, collaborating with cross-functional teams including design, verification, and software.Gather and analyze customer security requirements to define threat models and mitigation features for our computing systems, working alongside engineering teams to integrate these at the appropriate design levels.Qualifications:A Master’s degree in Electrical Engineering (MSEE) with 15+ years of relevant experience, or a PhD with 10+ years of applicable experience.Demonstrated expertise in multiple relevant domains, including computer architecture, secure computing, distributed systems, and datacenter reliability/manageability.Practical experience with authentication, isolation, encryption, and device signing.

At d-Matrix, we are on a mission to harness the power of generative AI and revolutionize technology. We stand at the cutting edge of software and hardware innovation, continuously exploring new frontiers of possibility. Our culture thrives on respect and collaboration.We embrace humility and prioritize direct communication. Our inclusive team values diverse perspectives, fostering enhanced problem-solving. We are in search of passionate individuals eager to tackle challenges and driven by results. Are you ready to explore your potential? Together, we can redefine the limitless opportunities of AI.Work Location:This is a hybrid position, requiring onsite work at our Santa Clara, CA headquarters 3-5 days per week.Key Responsibilities:• You will lead pre-silicon power estimation for design blocks, encompassing both RTL and physical design power assessments.• Collaborate with front-end and DV engineers to pinpoint power activity windows in designs, ensuring that feedback from estimations is effectively implemented to optimize power.• Develop an architectural power estimation tool tailored for AI workloads, calculating power based on system configuration and die-level metrics, including workload profiling with respect to memory size, bandwidth, and gate counts of compute/memory blocks.• Work alongside frontend architects and backend designers to compile necessary performance monitoring capabilities, system requirements, and usage analysis, contributing to hardware enhancements and die modifications.• Integrate analysis feedback into design processes with the frontend team.• Design micro-architecture and RTL, perform synthesis, and verify logic and physical power performance using state-of-the-art CAD tools and semiconductor technologies.• Design and implement performance enhancement and power-saving/monitoring functions that facilitate efficient design, testing, and debugging, participating in silicon bring-up and validation.Qualifications:• Master's degree in Electrical Engineering, Computer Engineering, or Computer Science with 10-15 years of relevant industry experience or equivalent.• Strong understanding of power, performance, micro-architecture, RTL, and physical design, with a focus on digital systems and IC design.

At d-Matrix, we are dedicated to unlocking the potential of generative AI, driving the transformation of technology. Our commitment to innovation in both software and hardware positions us at the forefront of industry advancements. We foster a culture of respect and collaboration, where humility, direct communication, and inclusivity are core values.We are in search of passionate individuals who are eager to embrace challenges and are motivated by effective execution. Are you ready to join us in exploring the vast possibilities of AI? Together, we can redefine the future!Location:This is a hybrid role, requiring on-site work at our Santa Clara, CA headquarters 3-5 days per week.Key Responsibilities:• Lead the micro-architecture and design of AI Control subsystem modules, including Hardware Execution Engines.• Take ownership of design documentation, execution, and delivery of high-performance, area-efficient, and power-efficient RTL meeting design targets and specifications.• Design micro-architecture and RTL, perform synthesis, and conduct logic and timing verification using cutting-edge CAD tools and semiconductor technologies.• Develop and implement logic functions that facilitate efficient testing and debugging.• Participate in silicon bring-up and validation for owned blocks.