About the job
About OLIX
At OLIX, we are at the forefront of a technological revolution as we redefine the future of artificial intelligence. The rapid growth of AI has unveiled a significant gap in infrastructure; the pace at which we can develop chips and power stations is no longer sufficient. The industry is still reliant on outdated hardware architectures that have reached their limits. We are pioneering a new paradigm that promises unparalleled speed and efficiency, representing the most significant economic opportunity of the next century. Our innovative Optical Tensor Processing Unit (OTPU) delivers performance and energy efficiency that existing chips cannot match.
The Role:
We are looking for a highly skilled Senior Staff FPGA Engineer to spearhead the architecture, design, and technical direction of FPGA-based systems within our OTPU platform. This senior individual contributor role is focused on system-level ownership, cross-functional technical leadership, and architectural decision-making. You will define high-performance FPGA subsystems, including high-speed interfaces, precision timing and synchronization, transceivers, and signal processing pipelines. Close collaboration with ASIC, hardware, optical, and software teams will be essential in driving coherent system design, mitigating risks in silicon development, and delivering production-grade solutions.
Responsibilities
- Define and take ownership of FPGA architecture for high-performance, high-bandwidth systems.
- Lead the design and optimization of high-speed interface subsystems (PCIe Gen4, multi-lane transceivers operating at >25 Gb/s NRZ).
- Architect deterministic timing and synchronization strategies across complex multi-device systems.
- Drive FPGA-based prototyping efforts to support silicon development and system validation.
- Establish design methodologies, coding standards, and verification strategies, guiding the implementation of robust error detection and correction mechanisms (ECC, including SECDED).
- Collaborate with software teams to define hardware-software interfaces and system control models.
- Lead system-level debugging of complex hardware-software interactions.
- Mentor engineers and provide technical leadership across FPGA development efforts.
- Identify performance bottlenecks and advocate for architectural improvements.
- Maintain a deep awareness of advancements in FPGA architectures and high-speed digital design.

