About the job
Join OLIX: Pioneering the Future of AI Hardware
At OLIX, we are at the forefront of addressing the unprecedented growth of AI technology, which is reshaping industries and demanding a revolution in hardware infrastructure. Our flagship innovation, the Optical Tensor Processing Unit (OTPU), represents a paradigm shift in chip design, offering unparalleled performance and energy efficiency that current technologies cannot achieve.
Your Role as a Staff Electronics Engineer
We are on the lookout for a talented Staff Electronics Engineer to spearhead the development of high-speed, mixed-signal, and compact power electronics that are integral to OLIX’s optical compute platforms. In this role, you will collaborate closely with teams across ASIC, FPGA, Optical, Mechanical, Firmware, and Systems to deliver cutting-edge, energy-efficient hardware solutions, including PCIe-based platforms and integrated systems operating at speeds exceeding 25–56Gb/s.
You will report directly to the Electronics Engineering Manager, taking on both hands-on execution and strategic technical leadership in board-level and subsystem design.
Key Responsibilities
Architect and guide the technical direction of intricate high-layer-count PCBs and accelerator subsystems.
Develop and implement signal integrity and power integrity strategies across entire product lines.
Lead initiatives focused on energy-efficient hardware design and optimization of performance-per-watt.
Conduct schematic and layout reviews, providing mentorship in high-speed design best practices.
Oversee the complete product-level hardware development process from concept to production independently.
Serve as a technical authority in cross-functional design discussions.
Design and develop high-speed multilayer PCBs supporting serial interfaces such as PCIe Gen4/Gen5 and SERDES-based links.
Implement and validate high-current, low-voltage power delivery systems for ASICs and FPGAs.
Perform comprehensive signal integrity (SI) and power integrity (PI) analysis during schematic and layout phases.
Define PCB stack-ups, routing constraints, impedance control strategies, and return path methodologies.

