Senior Software Engineer - Hardware Testing

About Our TeamAt OpenAI, our Hardware organization is at the forefront of developing cutting-edge silicon and system-level solutions tailored for the specific demands of advanced AI workloads. Our team is dedicated to creating the next generation of AI-native silicon, collaborating closely with software and research partners to co-design hardware that is seamlessly integrated with AI models. We not only deliver production-grade silicon for OpenAI’s supercomputing infrastructure but also innovate custom design tools and methodologies that drive acceleration and optimization specific to AI.About This RoleAs a member of our hardware optimization and co-design team, you will play a crucial role in co-designing future hardware from various vendors, focusing on programmability and high performance. You will partner with our kernel, compiler, and machine learning engineers to comprehend their distinct requirements concerning ML techniques, algorithms, numerical approximations, programming expressivity, and compiler optimizations. Your advocacy for these constraints will help shape and influence future hardware architectures aimed at efficient training and inference for our models. If you are passionate about efficiently distributing large language models across devices, optimizing system-wide networking bottlenecks, and customizing the compute pipeline and memory hierarchy of hardware platforms while simulating workloads at various abstraction levels, then this opportunity is perfect for you!This position is based in San Francisco, CA, utilizing a hybrid work model of three days in the office each week, with relocation assistance available for new hires.Key Responsibilities:Collaborate on the co-design of future hardware focusing on programmability and performance with hardware vendors.Support hardware vendors in developing optimal kernels and integrating support within our compiler.Generate performance estimates for critical kernels across diverse hardware configurations, influencing decisions regarding compute core and memory hierarchy features.Create system performance models at various abstraction levels and conduct analyses to guide decisions on scaling and front-end networking.Engage with machine learning engineers, kernel engineers, and compiler developers to align on high-performance accelerator needs.Facilitate communication and coordination with internal and external partners.Shape the roadmap for hardware partners to optimize their products for our AI capabilities.

About Our TeamJoin OpenAI’s innovative Hardware team, where we are redefining the landscape of silicon and system-level solutions tailored to the specific demands of cutting-edge AI workloads. Our mission is to design the next generation of AI-native silicon, collaborating closely with software and research teams to co-create hardware that seamlessly integrates with advanced AI models. Beyond developing production-grade silicon for OpenAI’s supercomputing infrastructure, we also craft bespoke design tools and methodologies that drive innovation and optimize hardware specifically for AI applications.About the RoleWe are seeking a passionate Junior RTL Engineer to contribute to the design and implementation of critical compute, memory, and interconnect components for our custom AI accelerator. You will engage closely with architecture, verification, physical design, and machine learning engineers to translate complex AI workloads into efficient hardware architectures. This hands-on role offers substantial ownership over the design definition, modeling, and implementation processes.This position is based in San Francisco, CA, utilizing a hybrid work model with three days in the office each week. Relocation assistance is available for new hires.Key ResponsibilitiesDevelop clean, production-quality microarchitecture and RTL for major accelerator subsystems.Engage in architectural studies, including performance modeling and feasibility assessments.Collaborate with software, simulator, and compiler teams to ensure effective hardware/software co-design and workload optimization.Work with design verification and physical design teams to ensure functional correctness, timing closure, and adherence to area/power specifications.Create and review performance and functional models to validate design intent.Participate in design reviews, documentation processes, and provide support throughout the silicon lifecycle.Ideal Candidate ProfileGraduate-level research or industry experience in computer architecture, AI/ML hardware-software co-design, encompassing workload analysis, dataflow mapping, or accelerator algorithm optimization.Proficient in writing production-quality RTL in Verilog/SystemVerilog, with a proven track record of delivering complex blocks to tape-out.Experience in developing hardware design models or architectural simulators, particularly in AI/ML or high-performance computing domains.Familiarity with industry-standard design tools and methodologies (lint, CDC/RDC, synthesis, STA).Strong analytical and problem-solving skills with a collaborative mindset.

Why Join Flux?At Flux, we are redefining hardware development by introducing the pioneering AI Hardware Engineer. Our mission is to democratize cutting-edge hardware creation and transform the global landscape of electronics design and manufacturing.Your RoleWe are seeking a seasoned leader in electrical engineering to spearhead our hardware design practices and principles. You will play a crucial role in enhancing our ECAD tool's capabilities and ensuring the integrity of our AI Hardware Engineer's knowledge and design strategies. Collaborating closely with product leadership, you will help shape and prioritize the advancement of AI capabilities, evaluation frameworks, and scalable strategies that empower our community to execute successful PCB projects. This position offers the opportunity to expand our Hardware Design function and team significantly.This is a high-impact, multidisciplinary role ideal for someone with a proven track record of developing complex electronics for mass production, such as smartphones, wearables, high-performance computing devices, networking equipment, and robotics, who enjoys translating real-world engineering challenges into innovative tools and AI functionalities.Key ResponsibilitiesLead ECAD Feature Development – Define product requirements for essential ECAD functionalities including placement/routing, constraints management, stackup, impedance control, DRC/DFM, manufacturing outputs, and prototyping workflows. Collaborate on specifications, validate through internal testing, beta programs, and comprehensive user feedback.Collaborate with AI/ML Teams – Educate the world’s first AI hardware engineer on effective product design practices. Establish best practices, guidelines, and evaluation frameworks; curate datasets; assess AI-generated designs; and cultivate the AI expertise to enable successful hardware production from the first run, avoiding common pitfalls.Enhance the Hardware Design Team – Start as an active manager overseeing two team members, progressively refining the team's responsibilities and scaling to create reference designs, demos, product specifications, training materials, and feedback mechanisms.Prototype Real Hardware – Oversee rapid prototyping (from schematic to realization) to showcase product/AI capabilities. Instrument designs for signal integrity, power integrity, and thermal validation; utilize data to close the feedback loop.Enhance User Experience – Take ownership of and improve current user experience metrics, feedback loops, and user engagement processes to inform our iterative product development.

About Our TeamAt OpenAI, our Hardware team is at the forefront of developing cutting-edge silicon and comprehensive system solutions tailored to the specific needs of advanced AI workloads. We pride ourselves on crafting the next generation of AI-native silicon, collaborating closely with software engineers and research teams to ensure our hardware is seamlessly integrated with AI models. Our mission extends beyond creating production-grade silicon for OpenAI’s supercomputing infrastructure; we also innovate custom design tools and methodologies that spark innovation and enable hardware specifically optimized for AI.About the RoleAs a Software Engineer on the Scaling team, you will play a pivotal role in designing and optimizing the foundational stack that manages computation and data flow across OpenAI’s supercomputing clusters. Your responsibilities will include crafting high-performance runtimes, developing custom kernels, enhancing compiler infrastructure, and building scalable simulation systems to validate and optimize distributed training workloads.This position requires you to work at the intersection of systems programming, machine learning infrastructure, and high-performance computing, where you will create intuitive developer APIs alongside highly efficient runtime systems. You will balance usability and introspection with the imperative for stability and performance across our dynamic hardware landscape.This role is based in San Francisco, CA, featuring a hybrid work model (three days in-office per week). Relocation assistance is provided.Key Responsibilities:Design and implement APIs and runtime components to efficiently manage computation and data movement for diverse ML workloads.Enhance compiler infrastructure by developing optimizations and compiler passes to accommodate evolving hardware advancements.Engineer and refine compute and data kernels, ensuring precision, high performance, and compatibility across simulation and production settings.Analyze and optimize system bottlenecks, focusing on I/O, memory hierarchy, and interconnects at both local and distributed scales.Create simulation infrastructure to validate runtime behaviors, test modifications to the training stack, and support the early development of hardware and systems.Quickly deploy updates to runtime and compiler across new supercomputing builds in close collaboration with hardware and research teams.Work across a varied tech stack, primarily utilizing Rust and Python, with a chance to influence architectural decisions within the training framework.

Join Our Innovative Team at Atomic SemiAt Atomic Semi, we are pioneering the future of semiconductor manufacturing with our state-of-the-art, compact fabrication facilities.Our approach leverages current technologies and innovative simplifications, enabling us to create our own tools for rapid iteration and enhancement.We are assembling a select group of exceptional engineers—mechanical, electrical, hardware, computer, and process specialists—who will take ownership of the entire stack from atomic structures to architectural designs. Our optimistic team is dedicated to advancing technology boundaries.We believe that smaller, faster, and self-built solutions are the key to success.Our facility is equipped with 3D printers, a variety of microscopes, e-beam writers, and general fabrication equipment. If there’s something we need, we’ll innovate to create it.Founded by Sam Zeloof and Jim Keller, our team combines practical chip-making experience with decades of industry leadership.Role OverviewAs an Electronic Hardware Design Engineer, you will collaborate with a talented team to design cutting-edge lithography systems, deposition tools, vacuum chambers, and high-precision motion control systems. You will tackle challenges, prototype innovative solutions, and bring your designs to production, contributing to transformative advancements in integrated circuit manufacturing.Your projects may involve high-voltage low-noise converters, motor drivers, attofarad sensors, and millikelvin temperature controllers—all in a single initiative.

Astranis is pioneering the development of advanced satellite systems designed to operate in high orbits, significantly enhancing humanity's capabilities in space exploration. Our satellites deliver dedicated and secure networking solutions to a diverse range of sophisticated clients, including large corporations, government entities, and the US military. With five satellites already in orbit and a robust pipeline of future launches, we are addressing a substantial backlog of over $1 billion in commercial contracts.Renowned for our unwavering commitment to uptime, data security, network transparency, and tailored solutions, Astranis has successfully secured over $750 million in funding from esteemed investors such as Andreessen Horowitz, Blackrock, and Fidelity. Our team consists of 450 talented engineers and entrepreneurs who design, construct, and manage our satellite systems from our expansive 153,000 sq. ft. headquarters located in Northern California, USA.Position: Hardware Design Associate, Software Defined Radio Team (Summer 2026)This Associate Engineer role is a twelve-week, salaried position intended for individuals who have completed a bachelor’s degree (or will have done so before starting at Astranis).As an Associate Engineer, you will have the incredible opportunity to tackle complex challenges. We take pride in empowering all team members at Astranis to engage in impactful work on significant projects, with our Associate Engineers addressing tasks that are equally pivotal and demanding as those assigned to our full-time staff. Many of our previous Associate Engineers have contributed to the design and testing of hardware and software destined for our inaugural satellite, with numerous alumni now working full-time at Astranis.If you are currently a college student, we encourage you to apply for an internship instead.Key ResponsibilitiesDesign, simulate, implement, and test our proprietary software-defined radio hardware.Perform hardware bring-up and debugging in the lab using cutting-edge instruments and equipment.Develop code to assess performance and automate the testing of satellite hardware.Collaborate closely with team members to integrate these systems into spacecraft.QualificationsA strong passion for hardware development, including hands-on design and development in a fast-paced environment.A Bachelor’s degree in Electrical Engineering or a related field.Proven ability to design, build, and test PCBAs from the ground up, demonstrated through student design team projects or competitions.

Fastly seeks a Staff Hardware Design Engineer to influence the hardware foundation of its global network. This position centers on creating and refining hardware systems that support the performance and reliability of Fastly’s infrastructure. Key responsibilities Design and develop hardware systems that enable Fastly’s network operations. Partner with teams across disciplines to shape and improve hardware designs. Apply technical knowledge to strengthen hardware capabilities. Assist with the rollout and deployment of new hardware solutions. Locations Denver, CO New York City, NY San Francisco, CA

Why Join Flux?At Flux, we are revolutionizing hardware development by creating the world's first AI Hardware Engineer. Our mission is to democratize access to cutting-edge hardware technology and transform how electronics are conceived and manufactured globally.Role OverviewAs a Software Engineer focusing on Agentic Development, you will be integral in building the core intelligence of our platform. You will develop innovative workflows, reasoning graphs, and seamless integrations that empower both novice users to transform ideas into manufacturable hardware and experienced electrical engineers to learn from past production challenges.Your role will uniquely merge web engineering with AI system design, utilizing TypeScript and LangGraph to embed smart functionalities directly into our design environment.Key ResponsibilitiesCraft agentic reasoning capabilities using TypeScript (LangGraph).Incorporate AI functionalities into the Flux web application (React/Redux) and Chat UI.Implement telemetry and logging systems to monitor runtime health, performance, and cost efficiency.Collaborate with product and electrical engineers to enhance intelligent ECAD workflows.Design and evaluate experiments; convert insights into actionable engineering decisions.Contribute to the development of agentic patterns, conventions, and best practices across the engineering organization.

Astranis is revolutionizing satellite technology by constructing cutting-edge satellites designed for high orbits, significantly enhancing humanity's capabilities in space exploration. Our satellites deliver dedicated, secure communication networks to a diverse clientele, including large corporations, government entities, and the U.S. military. With five satellites successfully launched and a robust pipeline of contracts worth over $1 billion, Astranis is at the forefront of satellite communications.As the preferred partner for clients with demanding requirements for reliability, data security, network visibility, and customization, we have attracted over $750 million in investments from prestigious firms like Andreessen Horowitz, Blackrock, and Fidelity. Our headquarters, spanning 153,000 square feet in Northern California, is home to a talented team of 450 engineers and entrepreneurs who design, build, and operate our satellites.Hardware Design Intern - Software Defined Radio Team (Summer 2026)Join us for a twelve-week internship that offers an invaluable opportunity for students currently enrolled in a four-year university program. At Astranis, we empower our interns to tackle significant challenges and contribute meaningfully to complex projects. Many of our past interns have played key roles in designing and testing hardware and software that are now operational on our first satellite, with many transitioning to full-time positions within the company.If you have already graduated from a four-year university, we encourage you to apply for the Associate Engineer position.

Join Plaud as the Head of Hardware Product Design, where you will lead a talented team of designers in creating innovative and high-quality hardware products. In this pivotal role, you will be responsible for driving the design strategy, ensuring that our products not only meet market needs but also enhance the user experience.

Astranis is at the forefront of satellite technology, dedicated to expanding humanity's presence in the solar system. Our advanced satellites operate in high orbits, delivering dedicated, secure networks to a diverse clientele that includes large enterprises, sovereign governments, and the US military. With five satellites currently in orbit and several more set to launch, we are excited to work through a robust backlog of over $1 billion in commercial contracts.Astranis is recognized as the premier satellite communications partner for clients with demanding standards for uptime, data security, network visibility, and customization. Having secured over $750 million from top-tier investors like Andreessen Horowitz, Blackrock, and Fidelity, our team of 450 engineers and entrepreneurs designs, builds, and operates our satellites from our expansive 153,000 sq. ft. headquarters in Northern California.Position: Senior Electrical Engineer - SDR Hardware DesignAs a Senior Electrical Engineer specializing in Software Defined Radio (SDR) Hardware at Astranis, you will spearhead the design, qualification, and testing of our bespoke software-defined radios. We seek innovative professionals skilled in creating cutting-edge high-speed hardware. If you think in terms of volts, bits, and dB's, this position is tailored for you! Collaborating with the RTL, Communications, and RF design teams, you will be instrumental in crafting superior radio systems for our payload and TTC systems.

Astranis is at the forefront of satellite technology, pioneering advanced satellites for high orbits that extend humanity's reach into the solar system. Our satellites deliver dedicated, secure networks to a diverse clientele, including large enterprises, sovereign governments, and the US military. With five satellites currently in orbit and numerous launches on the horizon, we are addressing a backlog exceeding $1 billion in commercial contracts.Astranis is the trusted satellite communications partner for clients demanding high uptime, robust data security, network visibility, and tailored solutions. We have secured over $750 million in funding from leading investors such as Andreessen Horowitz, Blackrock, and Fidelity, and our team of 450 engineers and entrepreneurs operates from our expansive 153,000 sq. ft. headquarters in Northern California.Senior Hardware/Production Test Software EngineerWe are in search of an experienced and driven Hardware/Software Test Engineer to join our dynamic team. In this pivotal role, you will design high-level software architecture to facilitate vehicle integration and testing operations. You will collaborate with various engineering teams to develop and implement effective test plans and create software for automated testing at both component and integrated levels. Furthermore, you will refine specifications from electrical engineers to validate critical flight components and support all stages of development from proposal to successful testing and flight. Your contributions will also include implementing ground control and telemetry software and strengthening our team through recruitment and hiring initiatives.

About Our TeamAt OpenAI, the Fleet team is integral to maintaining the robust computing environment that fuels our groundbreaking research and innovative product development. We manage extensive systems encompassing data centers, GPUs, networking, and more, ensuring optimal performance, availability, and efficiency. Our efforts empower OpenAI’s models to function seamlessly at scale, supporting both internal R&D and external offerings like ChatGPT. We emphasize safety, reliability, and responsible AI deployment over unrestrained growth.About the RoleAs a Software Engineer on the Fleet Hardware team, you will play a crucial role in ensuring the reliability and uptime of OpenAI’s compute fleet. Minimizing hardware failures is essential for research training progress and service stability since even minor disruptions can lead to significant setbacks. With the increasing complexity of supercomputers, the pressure to maintain operational integrity has never been higher.This is a unique opportunity to be at the forefront of technology, pioneering solutions for troubleshooting advanced systems on a large scale. You will work with cutting-edge technologies and innovate solutions to ensure the health and efficiency of our supercomputing infrastructure.Our team empowers skilled engineers with a significant degree of autonomy and ownership, enabling them to drive impactful change. This role requires a keen focus on comprehensive system investigations and the development of automated solutions. We seek individuals who dive deep into problems, conduct thorough investigations, and create automation for large-scale detection and remediation.In this Role, You Will:Design and maintain automation systems for provisioning and managing server fleets.Develop tools to monitor server health, performance, and lifecycle events.Collaborate with teams across clusters, networking, and infrastructure.Partner with external operators to uphold high-quality standards.Identify and resolve performance bottlenecks and inefficiencies.Continuously enhance automation to minimize manual tasks.

About the TeamThe Scaling team at OpenAI forms the architectural and engineering foundation of our infrastructure. We innovate and implement advanced systems that facilitate the deployment and operation of next-generation AI models. Our responsibilities encompass system software, networking, platform architecture, fleet-level monitoring, and performance enhancement.About the RoleWe are seeking a skilled software engineer proficient in transforming early-stage, sometimes chaotic, pre-production hardware into stable, operational systems. You will be pivotal in bootstrapping, imaging, integrating with the Kubernetes control plane, and ensuring observability. Your role will bridge early hardware bring-up, provisioning automation, fleet and cluster management, and integration with lab or cloud services—effectively converting new SKUs into usable capacity for our internal stakeholders.Key ResponsibilitiesManage the comprehensive bring-up and bootstrapping process for new systems and compute nodes, transitioning from bare metal or early access in lab or production/cloud settings to schedulable fleet capacity, including image building, user-data/configuration, cluster joining, and readiness gates.Develop and uphold top-tier golden image and provisioning workflows across lab and production environments, collaborating with partner-provided base images while ensuring OS/version compatibility.Collaborate with partner teams to integrate nodes into our fleet infrastructure and Infrastructure as Code (IaC) pipelines (Terraform, Chef, etc.), guaranteeing that cloud resources align seamlessly with our internal lifecycle expectations.Work closely with scheduling and platform owners to ensure new hardware is accessible and properly scheduled, addressing pool definitions, network connectivity, routing, admission controls, and platform-specific requirements.Ensure registration and inventory accuracy, providing hands-on support to track nodes and their metadata from end to end.Partner with teams to establish baseline health and telemetry monitoring for bring-up, including critical health signals, pass/fail assessments, and automated reporting for initial ramp decisions.Troubleshoot issues across various layers, including PXE/boot-loader, UEFI/BIOS, BMC, OS bring-up, NIC/network accessibility, kubelet/control-plane connectivity, storage limitations, and early lab/rack scenarios.

Who We AreSamsara (NYSE: IOT) is at the forefront of the Connected Operations™ Cloud, a transformative platform that empowers businesses reliant on physical operations to tap into Internet of Things (IoT) data. Our aim is to provide actionable insights that enhance safety, efficiency, and sustainability across vital industries such as agriculture, construction, transportation, and manufacturing. By digitally transforming these sectors, which represent over 40% of global GDP, we are contributing to a more efficient and sustainable economy.Joining Samsara means being part of a team that is defining the future of physical operations. You will engage in cutting-edge solutions, including Video-Based Safety, Vehicle Telematics, and Equipment Monitoring, within a supportive environment that fosters innovation and long-term impact.About the Role:We are seeking a Senior Hardware Systems Engineer to enhance our rapidly expanding product line. Your primary responsibility will involve leading the electrical engineering components of product architecture and design, grounded in comprehensive feasibility, design, and cost analyses. This encompasses critical aspects such as component selection, thermal management, and antenna design. You will leverage extensive telemetry and direct customer insights to inform and refine our product designs. Collaborating closely with Product Management, Firmware, and Hardware leadership, you will influence key engineering decisions while mentoring fellow engineers. The role will also require interaction with our US and Taiwan EE teams, as well as our Supply Chain and laboratory resources, to achieve our project goals effectively.This role is hybrid, requiring you to be in our San Francisco, CA office three days a week, with the flexibility to work remotely for two days. Travel may be necessary up to 25% of the time, and proximity to an international airport is essential. We offer relocation assistance for this position and welcome candidates from across the U.S. who are willing to relocate to the Bay Area.

About Our TeamThe Hardware team at OpenAI specializes in crafting custom silicon that fuels the most advanced AI systems globally. Our collaborative approach integrates system-level architecture with custom circuit designs, working closely with model and infrastructure teams to achieve remarkable breakthroughs in performance, power consumption, and efficiency across all layers of the technology stack.About the PositionWe are on the lookout for a talented Silicon Implementation Engineer with extensive knowledge in physical design and methodologies. As an integral part of our physical design team, you will play a crucial role in creating optimized datapath and interconnect solutions that enhance power, performance, and area (PPA) for cutting-edge AI accelerators.In this role, you will collaborate closely with RTL designers to establish and implement effective physical design strategies. You will be responsible for developing innovative tools, processes, and methodologies that boost team productivity. Your contributions will significantly influence silicon performance, cost efficiency, and the overall quality and speed of our team’s output.Key Responsibilities:Design, develop, and manage tools, processes, and methodologies for physical implementationOversee the physical implementation of floorplan blocks from initial floorplanning to final signoffWork in tandem with RTL designers to identify and implement optimal block solutionsEvaluate and enhance designs for timing, power, and area trade-offs, in collaboration with EDA vendors and ASIC partnersRequired Qualifications:Bachelor's degree with 4+ years, Master's with 2+ years, or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology developmentProven track record of successfully taping out complex silicon designsHands-on experience with block-level physical implementation and PPA optimizationProficient in coding with Python, Bazel, and TCLSolid experience in developing physical design tools, processes, and methodologiesStrong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification, and timing closureIn-depth knowledge of industry-standard tools and processes for physical synthesis, PNR, LEC, and power estimationPreferred Qualifications:Experience with AI or HPC-focused chipsExpertise in optimizing PPA for high-performance applications

About GridwareGridware is an innovative technology firm headquartered in San Francisco, committed to safeguarding and enhancing the reliability of the electrical grid. We have pioneered a revolutionary approach to grid management known as Active Grid Response (AGR), which meticulously monitors the electrical, physical, and environmental factors influencing grid safety and reliability. Our state-of-the-art AGR platform leverages high-precision sensors to identify potential issues at an early stage, facilitating proactive maintenance and fault resolution. This holistic strategy is designed to bolster safety, minimize outages, and ensure optimal grid performance. We are proud to be supported by prominent climate-tech and Silicon Valley investors. To learn more, visit www.Gridware.io.About the RoleWe are seeking a skilled Senior Hardware Reliability Engineer to lead reliability testing, analysis, and lifetime modeling of various outdoor electronic assemblies. This pivotal role will concentrate on the electronic components of our products, collaborating closely with our mechanical-focused Reliability Engineer and engaging with the broader hardware and cross-functional teams.

Company OverviewEcho Neurotechnologies is a pioneering startup specializing in Brain-Computer Interface (BCI) technology. We are committed to pushing the boundaries of innovation through state-of-the-art hardware engineering and artificial intelligence solutions. Our goal is to create transformative technologies that empower individuals with disabilities, enhancing their autonomy and overall quality of life.Team CultureBecome a part of our dedicated team of passionate and skilled professionals. In our dynamic early-stage environment, you will have the chance to influence key decisions that will have lasting impacts. We prioritize continuous learning and development, promoting cross-functional collaboration where your input is essential to our collective success.Role OverviewWe are on the lookout for a seasoned Senior Hardware Test Engineer to validate our custom Echo hardware systems. In this role, you will lead the testing processes for our specialized hardware devices and subsystems while developing and implementing custom test systems.Primary ResponsibilitiesConduct in-house design verification testsCoordinate testing with external laboratoriesCollaborate with the engineering team to create tailored testing solutionsWork alongside design engineers to characterize unique hardwarePrepare tests for vendor transfer

About Multiply LabsMultiply Labs is an innovative startup located in San Francisco, California, backed by renowned investors in technology and life sciences such as Casdin Capital, Lux Capital, and Y Combinator. Our goal is to develop the world's leading robotic systems and utilize them to make groundbreaking life-saving therapies accessible to everyone.We are transforming the manufacturing process of cell therapies through the creation of advanced robotic systems that automate and scale the production of these crucial treatments. Our cutting-edge robots enable biopharma companies to produce cell therapies efficiently without overhauling their existing processes, thus minimizing regulatory hurdles and risks. Unlike traditional methods that are labor-intensive and costly (often exceeding $1M per patient), our robotic solutions aim to make these vital treatments more affordable and reachable for those who need them.To discover more and view our robots in action, please visit www.multiplylabs.com and follow us on LinkedIn.Position OverviewWe are looking for a dedicated Hardware Reliability Engineer to become an essential part of Multiply Labs’ Reliability Engineering team. As a founding member, you will collaborate closely with the Hardware Product and Systems Integration teams to enhance our designs throughout the entire development lifecycle, from initial prototypes to fully deployed GMP production systems. Your contributions will directly support the delivery of life-saving therapies by ensuring our robots operate seamlessly within the high-stakes biotech environment.