Qualifications
• A Bachelor’s or Master’s degree in Engineering (B. Tech. / M. Tech.) with 5-8 years of relevant experience in Physical Design.• Proven experience in handling Netlist to GDS II processes at the block level across multiple tape-outs.• Strong proficiency in technology nodes including 28nm, 20nm, 14nm, and 10nm.• In-depth knowledge of EDA tools from Synopsys, Cadence, and Mentor, with specific experience in ICC, PTSI, Encounter, Nanoroute, Calibre, and StarRC.• Expertise in floorplanning, placement optimizations, clock tree synthesis (CTS), and routing.• Hands-on experience with block and top-level signoff Static Timing Analysis (STA), physical verification (DRC/LVS/ERC/antenna) checks, and reliability checks (IR/EM/Xtalk).• Familiarity with the physical implementation of timing and functional ECOs.• Comprehensive understanding of VLSI processes and device characteristics.• Proficiency in TCL and Perl scripting.
About the job
Join our dynamic Physical Design team at FiniteHR Consulting, where you'll engage in innovative projects within the GHz frequency range and cutting-edge technologies. As a Physical Design Engineer, you will play a pivotal role in the Physical Design process at both the Full Chip and block levels, focusing on advanced technologies such as 28nm and 14nm nodes.
Your key responsibilities will include overseeing the entire Physical Design workflow, from synthesis to place and route (PnR), ensuring Physical Verification closure for SoC and sub-chips. You will utilize your expertise to drive efficient design solutions and contribute to the success of our projects.