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Senior Physical Design Engineer

EtchedAustin
On-site Full-time

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Experience Level

Mid to Senior

Qualifications

Qualifications:5-10+ years of relevant experience in Physical Design engineeringDeep knowledge of design tools and methodology, from RTL synthesis to GDSII sign-offExperience with back-end design and timing closure on advanced process nodes (5nm and lower)Proficiency in Cadence and Synopsys tools for automated design flowsFamiliarity with various sign-off toolsExperience in low power design methodology and various design analysesHighly creative and innovative thinker

About the job

About Etched

Etched builds the first AI inference system tailored for transformers, delivering over 10x higher performance with lower cost and latency than conventional approaches. The company’s ASIC technology powers advanced products, from real-time video generation to sophisticated reasoning agents. Backed by leading investors and staffed by top engineers, Etched is focused on reshaping the infrastructure that supports the fast-moving AI sector.

Role Overview

The Senior Physical Design Engineer will play a central role in block-level implementation and verification. This position focuses on driving timing closure and optimizing power, performance, and area (PPA). The engineer will oversee third-party design partners and help refine internal workflows to accelerate design cycles.

What You Will Do

  • Develop a deep understanding of physical design challenges and solutions
  • Run physical design flows to achieve block closure, improve ASIC infrastructure, and automate design steps
  • Work closely with RTL designers, offering feedback to improve PPA
  • Create dashboards to monitor project convergence in physical design
  • Refine tool flows and collaborate with EDA vendors to adopt new technologies
  • Take responsibility for achieving block-level closure
  • Manage relationships with third-party physical design service providers

Who We’re Looking For

  • 5 to 10+ years of hands-on experience in physical design
  • Strong background in tools, flows, and methodologies from RTL synthesis through GDSII sign-off
  • Proven track record in back-end design and timing closure on advanced nodes (5nm and below)
  • Familiarity with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows
  • Experience using sign-off tools such as PrimeTime, Tempus, Voltus, and similar
  • Knowledge of UPF-based low power design, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
  • Creative thinker with strong problem-solving skills

Location

Austin

About Etched

Etched is at the forefront of AI technology, focusing on creating solutions that significantly enhance performance and reduce costs in AI inference systems. With a vision to lead the transformation of the AI infrastructure landscape, we are supported by distinguished investors and a team of top engineers dedicated to innovation and excellence.

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