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Senior/Lead Design Engineer - IP/SoC RTL

On-site Full-time

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Experience Level

Mid to Senior

Qualifications

Desired Skills and Experience:B. Tech or M. Tech with 6 to 8 years of relevant experience. Proficiency in logic design, micro-architecture, and RTL coding is essential. Expertise in Verilog is required. Familiarity with AMBA protocols such as AXI, AHB, and APB. Experience in synthesis and understanding of timing concepts for ASIC is required. Design experience with DDR, USB, or PCIe controllers is advantageous. Hands-on experience with multi-clock designs and asynchronous interfaces is a must. Knowledge of tools utilized throughout all phases of ASIC development (Lint, CDC, Simulation, etc.) is mandatory. Knowledge of low power design concepts is a plus.

About the job

SeviTech is seeking a skilled Senior/Lead Design Engineer specializing in IP/SoC RTL. In this pivotal role, you will drive the micro-architecture development and RTL coding at the IP/sub-system level.


Key Responsibilities:

  • Develop micro-architecture and RTL for IP/sub-systems.
  • Establish block/sub-system level timing constraints.
  • Integrate IP/sub-systems effectively.
  • Conduct basic verification within an IP Verification environment or via FPGA.

About SeviTech Systems

SeviTech Systems is a forward-thinking technology company focused on delivering innovative solutions in the semiconductor industry. Our commitment to excellence drives us to seek top talent to join our team and contribute to groundbreaking projects.

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