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Physical Design and Verification Engineer

NeuralinkAustin, Texas, United States; Fremont, California, United StatesNew
On-site Full-time $158K/yr - $243K/yr

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Experience Level

Mid to Senior

Qualifications

Required Qualifications:Bachelor of Science (B. S.) in Electrical Engineering, Computer Science, or a related discipline, or equivalent practical experience. A minimum of 5 years of expertise in digital physical design and verification. Proven proficiency in the complete RTL to GDSII flow and extensive experience utilizing industry-standard Electronic Design Automation (EDA) tools for physical design and timing signoff. In-depth understanding of industry standards and practices in physical design, including physically-aware synthesis flow, floor-planning, place & route, metal fill, chip finishing, signal integrity checks, dynamic EMIR-Drop analysis, and formal ESD verification. Experience with signoff ECO flow to address timing, noise, IR-Drop, and EMIR violations. Experience in physical design verification to resolve LVS/DRC/PERC issues at both the chip and block levels using standard industry tools. Proficiency in developing automation flows and scripts using Python, Perl, Makefile, Tcl, and UNIX shell. Preferred Qualifications:Master of Science (M. S.) in Electrical Engineering, Computer Science, or a related field, or equivalent experience. Experience in the physical design and implementation of complex ASIC systems at advanced technology nodes, preferably at 16nm and below. Familiarity with DFT (Design For Test) flows and ATPG methodologies. Knowledge of I/O design flow in multi-voltage power domains.

About the job

Neuralink develops devices that connect directly with the human brain. The company’s technology focuses on restoring movement for people with paralysis, improving vision for those with impairments, and changing how people interact with digital systems.

The Brain Interfaces Hardware Department leads the design of chip architecture and silicon systems for neural recording and stimulation. This group works on system-on-chip (SoC) solutions that support high-bandwidth brain-machine interfaces. Team members include engineers committed to advancing neurotechnology.

Role overview

The Physical Design and Verification Engineer manages the full physical design flow from RTL to GDSII. This includes:

  • Synthesis
  • Placement
  • Clock tree synthesis
  • Detailed routing
  • Optimization
  • Physical signoff verification

Locations

This position is based in Austin, Texas or Fremont, California.

About Neuralink

Neuralink is on a mission to revolutionize the interaction between humans and technology through groundbreaking neurotechnology. Our team is committed to developing advanced neural interfaces that empower individuals and redefine cognitive capabilities.

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