Math Content Teacher

About EtchedEtched is pioneering the development of the world's first AI inference system specifically designed for transformer architectures, achieving over 10x greater performance and significantly reduced costs and latency compared to conventional solutions like the B200. With Etched's custom ASICs, you can create innovative products that were previously unattainable with GPU technology, such as real-time video generation models and advanced deep reasoning agents. Supported by substantial investments from top-tier venture capitalists and a team of elite engineers, Etched is transforming the foundational technology layer for the most rapidly evolving sector in history.Job SummaryWe are on the lookout for a talented and driven Post-Silicon Validation Engineer to become part of our vibrant team. The successful candidate will play a pivotal role in bringing up, validating, and characterizing ASICs from the initial silicon phase through to the production ramp-up. This critical position ensures the functional accuracy, performance integrity, and reliability of our advanced AI and machine learning accelerator hardware, facilitating the successful launch of our innovative products.

Join Lumilens as the Director of Silicon Test Engineering, where you'll lead a talented team in the development of cutting-edge silicon testing strategies. In this pivotal role, you will oversee the design, implementation, and optimization of test processes to ensure the highest quality standards are met. Your leadership will directly contribute to the advancement of our innovative technologies.

Join our team as a Validation Engineer specializing in Media Stack Validation. In this role, you will be responsible for ensuring the integrity and performance of our media validation processes. You will work closely with cross-functional teams to identify issues and enhance system efficiencies.

We are seeking a talented Power Integrity Engineer to join our innovative team at Lumilens in San Jose, California. In this role, you will be responsible for ensuring the integrity of power systems within silicon components, contributing to the advancement of our cutting-edge technology.As a Power Integrity Engineer, you will work closely with cross-functional teams to analyze and optimize power distribution networks, develop simulations, and conduct testing to ensure product reliability. Your expertise will play a crucial role in delivering high-performance solutions that meet our clients' needs.

etched seeks a Systems Validation Engineer (Level 10) based in San Jose. This position centers on ensuring that systems operate reliably and consistently meet performance targets. Key responsibilities Develop and execute validation protocols for both new and existing systems Review and interpret system performance data to identify issues and suggest improvements Collaborate with engineering, product, and quality teams to enhance product reliability Role impact The work in this role directly influences the quality and dependability of etched’s products. Effective validation helps ensure solutions perform as intended and align with customer expectations.

Role overview Etched seeks a PCIe Validation Engineer based in San Jose. This position centers on hands-on validation and testing of PCIe products, ensuring their integrity and reliable performance. The work directly influences the quality of PCIe solutions delivered to customers. What you will do Validate and test multiple PCIe protocols through hands-on methods Review and analyze test results to spot issues or performance limitations Collaborate with engineers from other teams to enhance product quality

About EtchedEtched is pioneering the development of the world's first AI inference system specifically designed for transformers, achieving over 10x higher performance along with significantly reduced costs and latency compared to traditional solutions like B200. Our cutting-edge ASIC technology empowers the creation of products that were previously unfeasible with GPUs, enabling real-time video generation models and highly advanced deep reasoning agents. Supported by substantial investments from top-tier investors and staffed by leading engineers in the industry, Etched is at the forefront of revolutionizing the infrastructure layer for the fastest-growing sector in history.Job OverviewWe are on the lookout for a skilled and enthusiastic Platform Validation Engineer to join our team. In this role, you will focus on validating the functionality of system hardware and printed circuit boards (PCBs), ensuring optimal power and signal integrity across all interfaces. Your responsibilities will include collecting and analyzing lab data to verify hardware performance, supporting post-silicon characterization, and guaranteeing reliable operation across multiple subsystems, such as PCIe and I2C.Key ResponsibilitiesConduct thorough system hardware and PCB functional verifications to ensure all features align with design specifications, including validation of power and signal integrity margins.Gather and analyze lab data to confirm power delivery, signal integrity, and the overall robustness of the system.Assist in post-silicon validation by identifying critical performance metrics and performing PVT, power, and thermal characterizations.Assess PCIe performance, focusing on signal integrity, eye opening measurements (EOM), and bit error rate (BER) to ensure sufficient operating margins.Detect hardware issues, execute root cause analyses, and facilitate resolutions in collaboration with cross-functional teams.Design and implement DOE experiments to troubleshoot hardware problems and enhance system performance.Validate power sequencing, microcontroller functionality, and perform analyses on power efficiency, noise, and transients.Conduct detailed characterizations of I2C bus systems to ensure compliance with design requirements.Document and track PCB issues and validation results, ensuring effective communication with relevant stakeholders.Work closely with design, firmware, and system engineering teams to guarantee comprehensive hardware quality.

Astera Labs (NASDAQ: ALAB) builds rack-scale AI infrastructure by developing advanced connectivity solutions. The company works with hyperscalers and partners across the ecosystem to help organizations make the most of modern AI. Astera Labs' Intelligent Connectivity Platform integrates semiconductor technologies such as CXL®, Ethernet, NVLink, PCIe®, and UALink™ with the COSMOS software suite to support flexible, scalable connectivity systems. Role overview This Electrical Validation Engineer Internship for 2026 is located in San Jose, CA. The internship centers on post-silicon validation for connectivity products. Interns will take on lab-based challenges that require both hardware and software skills, contributing to real engineering projects. What you will do Support post-silicon validation activities for Astera Labs' connectivity solutions Troubleshoot and solve lab challenges involving hardware and software Work closely with cross-functional teams throughout the validation process Collaboration Interns will interact with engineers and other teams to address technical challenges and ensure product quality during validation.

Join Lumilens as a Senior/Principal Signal Integrity Engineer specializing in Silicon Photonics and AI Interconnects. In this pivotal role, you will collaborate with a talented team to innovate and develop cutting-edge solutions that enhance signal integrity in advanced photonic systems.Your expertise in high-speed digital and analog signal integrity analysis will be invaluable as you lead projects that bridge the gap between technology and application. You will be responsible for designing, modeling, and testing signal integrity for next-generation interconnects, ensuring optimal performance and reliability.

Astera Labs, based in San Jose, CA, creates connectivity solutions tailored for rack-scale AI infrastructure. The team works with technologies including CXL®, Ethernet, NVLink, PCIe®, and UALink™ as part of its COSMOS software suite. These products support both standard and custom architectures for organizations building scalable systems for AI workloads. More information can be found at www.asteralabs.com. Role overview The Electrical Validation Engineer - NCG 2026 will contribute to the development and execution of electrical validation tests, measuring device performance across various system conditions. This role plays a key part in ensuring Astera Labs’ connectivity products for AI and Machine Learning meet strict parametric standards and customer requirements. What you will do Create validation strategies for new products after silicon fabrication Automate testing for integrated circuits and board-level products Design experiments to investigate and address unexpected device behaviors Collaborate with internal teams to assess performance margins and confirm compliance with specifications

Astera Labs, based in San Jose, CA, develops connectivity solutions for AI and cloud infrastructure. The company works closely with hyperscalers and technology partners to deliver products that help organizations scale and optimize AI workloads. Astera Labs' Intelligent Connectivity Platform integrates technologies like CXL, Ethernet, NVLink, PCIe, and UALink with the COSMOS software suite to support end-to-end connectivity in advanced systems. Both standards-based and custom solutions are available, allowing customers to tailor architectures for their infrastructure needs. Role overview The System Validation Engineer (NCG 2026) will focus on validating high-speed interconnects and AI fabrics in custom silicon. This role involves working with advanced technologies such as PCIe Gen5/Gen6, CXL, and memory-semantic fabrics. What you will do Participate in chip bring-up for new silicon products Debug and validate system-level functionality across multiple connectivity standards Work with technologies including PCIe Gen5/Gen6, CXL, and memory-semantic fabrics Requirements Interest in system validation for high-speed interconnects and AI infrastructure Familiarity with custom silicon or semiconductor technologies is helpful Located in or able to work from San Jose, CA To learn more about Astera Labs, visit www.asteralabs.com.

Join OKX as a Staff AI Engineer specializing in Model Post-Training and Alignment. In this pivotal role, you will lead initiatives that enhance the performance and alignment of AI models. You will work with cutting-edge technologies and collaborate with cross-functional teams to drive innovation in AI solutions.

Axiado is seeking a Senior FPGA/Emulation Validation Engineer based in San Jose. This position centers on validating and emulating FPGA designs to ensure they meet demanding standards for performance and reliability. Role overview The Senior FPGA/Emulation Validation Engineer plays a key part in the engineering team. The focus is on verifying that FPGA designs function as intended and support the development of advanced solutions. What you will do Validate FPGA designs for accuracy, performance, and reliability Emulate complex hardware systems to support ongoing development Contribute technical expertise to engineering projects that aim for high standards Location This role is based in San Jose.

Astera Labs (NASDAQ: ALAB) develops rack-scale AI infrastructure, offering advanced connectivity solutions for data centers and AI applications. The company partners with hyperscalers and industry leaders to enable organizations to maximize the potential of modern AI technologies. Its Intelligent Connectivity Platform brings together CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor technologies, integrated with the COSMOS software suite, to support diverse connectivity needs. Astera Labs also delivers custom solutions alongside its standards-based portfolio, helping clients build architectures suited to their specific requirements. More details can be found at www.asteralabs.com. Role overview This AI/ML Intern for Silicon Development Automation role is based in San Jose, CA. The internship centers on developing AI-driven workflows that accelerate silicon chip design. The work involves using generative AI and deep learning to enhance Electronic Design Automation (EDA) processes, with a particular emphasis on frontend design and verification. What you will do Support the creation of AI-powered automation for silicon development, including circuit design, verification, and debugging tasks. Assist in integrating EDA tools with large language model (LLM) capabilities.

United Firm seeks a Post Conviction Relief Attorney based in San Jose, CA. This position centers on criminal and immigration law, helping clients pursue post-conviction relief. The attorney will work closely with a Supervising Attorney and collaborate with a team of attorneys and legal assistants. Role overview Handle post-conviction relief cases from initial intake through final resolution Meet with clients, understand their situations, and guide them through the legal process Work with fellow attorneys and legal assistants to develop case strategies Take part in litigation and, when needed, appellate work Requirements Background in litigation or appellate law Interest in both criminal and immigration law Ability to collaborate effectively within a team Clear and strong communication skills for working with clients

Efficient is at the forefront of innovation, developing the world's most energy-efficient general-purpose computer processor. Our patented technology utilizes 100 times less energy than current leading ultra-low-power processors, all while being fully programmable with standard high-level programming languages and AI/ML frameworks. This exceptional efficiency allows for perpetual and pervasive intelligence, enabling AI/ML to operate continuously on a single AA battery for 5-10 years. Our platform's unprecedented efficiency empowers IoT devices to intelligently capture and curate first-party data, fueling the next major computing revolution.We are seeking a highly experienced Design Verification & Emulation Manager to lead, expand, and enhance our verification and emulation organization, a vital component of our newly established hardware engineering team. This high-impact leadership position is responsible for guaranteeing silicon correctness and system-level readiness across multiple industry-defining product lines. You will define the verification strategy from block-level to full-chip, spearhead emulation-based validation for early software enablement, and cultivate a world-class team of verification and emulation engineers.This position uniquely combines deep technical knowledge with strong leadership and program execution capabilities, making it ideal for an individual who excels at the intersection of architecture, verification methodology, hardware-software integration, and team development. This is a rare opportunity to influence our products and processes as we transition from initial product development to market launch and large-scale production. Join us to help shape the future of computing at the edge and beyond!

Founded in 2017, WeRide (NASDAQ: WRD) stands at the forefront of autonomous driving technology development, ranging from Level 2 to Level 4. As the only technology firm in the world with driverless permits across China, the UAE, Singapore, and the United States, WeRide is actively involved in autonomous driving research, testing, and operations across more than 30 cities in 10 countries. Our self-driving fleet has been operational for over 2,200 days, showcasing our commitment to innovation and excellence in this field.We invite enthusiastic new graduates to join our Silicon Valley Metrics Team as a Data Engineer. This role will play a vital part in advancing L3+ Advanced Driver Assistance Systems (ADAS) and L4 Autonomous Driving (AD) Systems. You will be responsible for developing scalable evaluation frameworks and crafting high-impact scenarios that foster continuous improvements in autonomous driving technology. The ideal candidate will possess a robust understanding of business requirements, data pipelines, and system behaviors, coupled with the ability to convert complex test data into actionable insights.

Astera Labs, listed on NASDAQ as ALAB, develops connectivity solutions that power AI infrastructure. The company partners with hyperscalers and others in the ecosystem to help organizations fully utilize modern AI. Their Intelligent Connectivity Platform combines semiconductor technologies like CXL®, Ethernet, NVLink, PCIe®, and UALink™ with the COSMOS software suite, supporting unified and flexible large-scale systems. More information is available at www.asteralabs.com. Role overview This Business Development Intern position for 2026 is based in San Jose, CA. The internship centers on AI hardware and custom silicon, making it a fit for those interested in technology and the challenges of scaling large systems. The role does not require deep technical expertise. Instead, it gives insight into how organizations assess partners for custom silicon projects and how technical concepts become actionable business strategies. Main responsibility Research trends in AI hardware, focusing on accelerators, connectivity solutions, and semiconductor technologies.

Etched develops AI inference systems designed specifically for transformer models. The company’s ASIC technology aims to deliver over 10x the performance of conventional systems, while reducing both cost and latency. This approach supports products that standard GPUs cannot handle, such as real-time video generation and advanced reasoning agents. Etched is backed by leading venture capital firms and staffed by experienced engineers focused on advancing AI infrastructure. Role overview The Director of Lab Operations leads the Platforms Validation lab at Etched’s San Jose location. This position oversees all operational aspects, from hardware intake and serialization to equipment setup and ongoing lab maintenance. The role manages workflow, coordinates board and component rework, supervises a skilled lab team, and is responsible for the physical infrastructure of the facility. Regular collaboration with the Head of Platform Validation Engineering ensures that lab operations stay aligned with engineering objectives and project timelines. What you will do Oversee hardware intake, serialization, and inventory management Coordinate and track rework for boards and components Maintain and enhance the physical lab environment and infrastructure Commission and set up lab equipment as required Supervise and support the lab staff Manage workflow to support efficient testing and validation Work closely with engineering leadership to align lab operations with project schedules Requirements Experience managing laboratory or technical infrastructure operations Background in team supervision or junior management Technical understanding of hardware validation workflows Ability to interpret schematics and follow bring-up sequences Experience overseeing PCB rework activities