About the job
About Neuralink:
At Neuralink, we are pioneering the development of advanced devices that create a seamless bi-directional interface with the human brain. Our groundbreaking technology aims to restore movement to individuals with paralysis, restore vision to the blind, and transform the way humans engage with the digital landscape.
Team Overview:
The Brain Interfaces Soc Department is at the forefront of chip architecture and silicon implementation for neural recording and stimulation systems-on-chip (SoC), tailored for high-bandwidth brain-machine interface applications. Our team consists of outstanding engineers dedicated to expanding the limits of current technology and shaping the future of neurotechnology.
Role Overview & Responsibilities:
As a Hardware and Software Co-Design Engineer, you will lead the design and implementation of micro-architecture and register-transfer level (RTL) digital IPs and systems, focusing on high-throughput, low-power digital signal processors (DSPs) and general-purpose hardware accelerators. You will play a crucial role in realizing cutting-edge brain-computer interfaces. We prefer candidates with a solid background in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC.
- Designing and implementing micro-architecture and RTL for:
- Low-power digital signal processors
- General-purpose hardware accelerators
- Graphics processing units
- Radio MAC/PHY interfaces
- Serial link MAC/PHY interfaces
- Collaborating with firmware engineers to optimize hardware/software interfaces
- Conducting application-specific architecture optimization, including:
- Complex system modeling for energy and performance benchmarks
- Workload analysis and modeling
- Energy/performance profiling and analysis
- Making architecture-level design trade-offs with process technology and workload types
- Balancing cost and performance in the face of manufacturing process variation
- Working closely with verification engineers on silicon bring-up tests

