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FPGA RTL Design Engineer / Senior Engineer

On-site Full-time

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Experience Level

Mid to Senior

Qualifications

• A Bachelor's or Master's degree in Electronics or a related field with 8 to 10 years of relevant experience.• Proven expertise in logic design, micro-architecture, and RTL coding is essential.• Proficiency in Verilog is mandatory.• Familiarity with AMBA protocols such as AXI, AHB, and APB is required.• Experience in synthesis and understanding timing concepts within Xilinx FPGA implementations is crucial. Prototyping with FPGAs is a must.• Knowledge in the design of complex protocols including DDR, USB, or PCIe controllers is an advantage.• Hands-on experience with multi-clock designs and asynchronous interfaces is necessary.• Familiarity with tools used in ASIC development phases such as Lint, CDC, and simulation is essential.• Understanding of low-power design concepts is a plus.

About the job

SeviTech Systems is seeking a talented and experienced FPGA RTL Design Engineer / Senior Engineer to join our innovative team.

As an integral part of our design team, you will be tasked with developing micro-architecture at the IP/sub-system level and executing RTL coding to create robust FPGA solutions.

Your responsibilities will include preparing timing constraints for block/sub-systems, integrating various IPs/sub-systems, and conducting verification processes in IP environments or FPGA setups.

About SeviTech Systems

At SeviTech Systems, we pride ourselves on delivering cutting-edge technology solutions and a collaborative work environment. Our team is dedicated to innovation and excellence, making significant contributions to the industry.

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