Principal Technical Program Manager - Hardware/Silicon

At d-Matrix, we are committed to unlocking the capabilities of generative AI, driving the next wave of technological transformation. As pioneers in both software and hardware innovation, we continuously challenge the limits of what technology can achieve. Our workplace thrives on respect and collaboration, fostering an environment where diverse perspectives contribute to superior solutions.We value humility and advocate for direct communication. Our inclusive team seeks individuals who are passionate about solving complex challenges and are motivated by achieving results. Are you ready to explore your potential? Together, let's shape the limitless future of AI.Location:We offer a hybrid work model, requiring on-site presence at our Santa Clara, CA headquarters 3-5 days per week.About the Role:We are on the lookout for a Principal Technical Program Manager to spearhead engineering excellence within our global hardware division. This position will emphasize the development of lightweight, scalable processes that ensure reliable project delivery in a fast-paced startup culture. You will collaborate with engineering leaders to translate corporate objectives into viable software programs, enhance planning and execution methodologies, and cultivate teamwork across various locations and technical disciplines. The ideal candidate will thrive in a dynamic, internationally distributed setting and will be dedicated to delivering high-quality software punctually.Your Responsibilities:Oversee comprehensive program management throughout the chip development lifecycle, including feature trade-offs among Product, Architecture, and Design teams; chip architecture, RTL design, design verification, emulation, modeling (power, performance), Design for Test (DFT), Static Timing Analysis (STA), physical design, packaging, analog circuit design, system design, and tapeout.Establish clear and predictable milestones for development involving the company and third-party partners for IPs, VIPs, and physical design.Coordinate project delivery among teams in North America and India.Define performance metrics, develop dashboards, and create reports to monitor progress and program health.Craft playbooks and establish best practices for program management across the organization to facilitate cross-functional deliveries.Identify potential risks to delivery schedules and quality, implementing mitigation strategies.Serve as a key communicator between hardware teams and company leadership, providing concise updates and insights.

At d-Matrix, we are dedicated to unlocking the potential of generative AI to drive technological transformation. Positioned at the cutting edge of both software and hardware innovation, we strive to redefine the limits of what is achievable. Our work culture is rooted in respect and collaboration.We champion humility and prioritize direct communication. Our inclusive team thrives on diverse perspectives that lead to superior solutions. We are on the lookout for individuals who are passionate about overcoming challenges and are driven by results. Are you ready to explore your playground? Together, we can shape the infinite possibilities of AI.Location:This position is hybrid, requiring 3-5 days per week onsite at our Santa Clara, CA headquarters.About the Role: As a Principal Technical Program Manager, you will spearhead engineering excellence across our global hardware organization. This pivotal role will focus on devising lightweight, scalable processes that ensure reliable project delivery in a rapidly growing startup environment. You will collaborate closely with engineering leaders to convert company goals into actionable software programs, enhance planning and execution practices, and promote collaboration across diverse geographies and technical domains. The ideal candidate will thrive in a fast-paced, globally distributed setting and possess a deep passion for delivering high-quality products punctually.Your Responsibilities:Oversee end-to-end program management throughout the post-silicon and system hardware development cycle:Prepare for silicon arrival by establishing lab spaces, setting up systems/boards, and managing production (EVK) design and validation across Silicon & Systems Hardware, Firmware, QA, and Manufacturing engineering teams.Lead firmware deployment and development to showcase all key features of the chip and systems.Conduct power and performance characterization, deliver demo versions, and initiate qualification processes including silicon qual, board qual, product qual, and NPI.Establish clear and predictable milestones for development within the company and with third-party partners.Coordinate project delivery across teams in North America, India, Serbia, and Australia.Define and track performance metrics, create dashboards, and generate reports to monitor progress and program health.

At Tenstorrent, we are at the forefront of pioneering AI technology that is transforming performance standards, enhancing user experience, and optimizing cost efficiency. As AI reshapes the computing landscape, our solutions are evolving to integrate advancements across software models, compilers, platforms, networking, and semiconductors. Our talented team has engineered a high-performance RISC-V CPU from the ground up, united by our passion for AI and our commitment to creating the most effective AI platform possible. We highly value collaboration, curiosity, and a relentless pursuit of innovative solutions. We are expanding our team and are eager to welcome contributors at all experience levels.The Technical Program Manager will be instrumental in steering the complete lifecycle of next-generation System on Chips (SoCs), guiding projects from the initial architecture phase through RTL, verification, DFT, physical design, tape-out, and post-silicon validation. This position demands a robust technical understanding of silicon development coupled with program management proficiency to ensure the successful execution of complex, cross-functional endeavors.This position is hybrid, based in Santa Clara, CA.We encourage applicants of varying experience levels for this role. During the interview process, candidates will be evaluated for the appropriate level, and offers will align with that level, which may differ from the one outlined in this posting.

At d-Matrix, we are dedicated to unlocking the transformative potential of generative AI to revolutionize technology. As pioneers in software and hardware innovation, we continuously push the boundaries of what's achievable. Our culture thrives on collaboration and respect.We hold humility in high regard and prioritize direct communication. Our inclusive team values diverse perspectives, fostering better solutions. We are on the lookout for passionate individuals who relish tackling challenges and are driven by results. Are you ready to explore your playground? Together, we can shape the limitless possibilities of AI.Location:Hybrid work arrangement, requiring onsite presence at our Santa Clara, CA headquarters 3-5 days per week.Role Overview: Principal Technical Program ManagerWe are in search of an experienced Principal Technical Program Manager to spearhead engineering excellence within our global software organization. This role emphasizes the establishment of streamlined, scalable processes to ensure predictable project delivery in a dynamic startup environment. You will collaborate with engineering leaders to translate organizational objectives into actionable software initiatives, enhance planning and execution practices, and promote cross-functional collaboration across various regions and technical areas. The ideal candidate should thrive in a fast-paced, globally distributed setting and possess a passion for delivering high-quality software punctually.Key Responsibilities:Oversee end-to-end program management across various software domains: ML, kernel, compiler, runtime, and tools.Facilitate delivery across distributed teams located in North America, India, Serbia, and Australia.Adopt agile methodologies tailored to a rapidly scaling startup.Establish metrics, dashboards, and reporting mechanisms to monitor progress and program health.Create playbooks and best practices for effective program management organization-wide.Convert product and business objectives into executable engineering programs.Proactively identify and mitigate risks to project timelines and quality.Serve as a liaison between software teams and senior leadership, delivering clear updates and insights.Collaborate with product, hardware, and partner teams to manage dependencies effectively.Qualifications:The ideal candidate will possess a strong background in technical program management, with experience in software development, project delivery, and agile methodologies. A proven track record of leading cross-functional teams and delivering high-quality software solutions in a timely manner is essential.

Join d-Matrix, a leader in generative AI technology, as we redefine the boundaries of software and hardware innovation. Our commitment to a culture of respect and collaboration drives us to push the limits of what's achievable in the tech landscape.At d-Matrix, we embrace humility and prioritize straightforward communication. Our inclusive team thrives on diverse perspectives, fostering innovative solutions. We are on the lookout for passionate individuals eager to tackle challenges and focused on execution. Ready to explore your potential? Together, we can shape the future of AI.Location: Hybrid, with a requirement to work onsite at our Santa Clara, CA headquarters 3-5 days a week.The Role: Principal Technical Program Manager – Software/ReleaseWe are in search of a dynamic Principal Technical Program Manager to spearhead engineering excellence and oversee the release management function across our global software organization. This pivotal role focuses on establishing lightweight, scalable processes that ensure reliable project delivery in a rapidly growing startup environment. You will serve as the operational bridge between Engineering, Product, QA, and IT, translating company goals into actionable software programs while managing the entire release lifecycle. The ideal candidate thrives in a fast-paced, globally distributed setting and is passionate about delivering top-notch software on schedule.Key Responsibilities:Release Management & Cross-Functional CoordinationManage End-to-End Release Cycles: Oversee the software release lifecycle from initial planning to final deployment, ensuring alignment with Engineering, Product Management, QA, and IT/DevOps regarding scope, dependencies, and timelines.Release Quality & Governance: Define and implement release criteria and quality standards, collaborating with QA to confirm comprehensive testing coverage and resolution of critical bugs before release.Stakeholder Management: Serve as the primary contact for all release-related communications, articulating release contents, status, risks, and

EnCharge AI stands at the forefront of advanced AI hardware and software systems, specializing in edge-to-cloud computing solutions. Our innovative in-memory computing technology delivers unprecedented compute efficiency and density, surpassing the capabilities of existing leading solutions. Our high-performance architecture, paired with seamless software integration, unlocks the vast potential of AI for applications where power, energy, and space are constrained. Established in 2022, EnCharge AI is guided by industry veterans with extensive experience in semiconductor design and AI systems.About the Position:As the Silicon Operations Manager, you will play a pivotal role in overseeing operational activities, from product definition to production ramp-up and sustained production. You will lead new product introduction initiatives, ensure operational readiness for production, and manage the product lifecycle. Reporting directly to the COO, you will be instrumental in the development, qualification, and manufacturing ramp-up of our cutting-edge silicon products.

About Us: nEye.ai is an innovative startup specializing in optical switch technology, committed to transforming the landscape of data centers. Through our advanced MEMS-based silicon photonics optical circuit switches (OCS), we effectively eliminate critical bottlenecks in AI processing, facilitating direct optical connections between thousands of GPUs and memory units. Our flagship product, the SuperSwitch, boasts ultra-low power consumption and high radix compact chip-scale design, significantly enhancing performance, efficiency, and scalability for hyperscale data centers. Job Overview: We are in search of a Principal Silicon Photonics Layout Engineer who will take charge of our design and tapeout processes for complex Photonic Integrated Circuits (PICs) using a code-based, functional layout approach. In this pivotal role, you will architect and sustain a robust script-based library of parametric components. You will effectively bridge the realms of optical physics and software engineering, ensuring that layouts are not only highly reproducible but also optimized for high-yield, production-scale fabrication. This position is particularly suited for candidates who view layout as a software engineering challenge and excel in a programmatic, automation-focused environment.

Join Kioxia America, Inc. as a Technical Ecosystem Program Specialist, where you will play a pivotal role in driving the success of our technical programs. You will collaborate with cross-functional teams to ensure seamless integration and delivery of our cutting-edge technologies.

Join PayNearMe as a Staff Technical Program Manager, where you'll spearhead our Quality and Reliability initiatives across vital systems and services. This impactful individual contributor position is tailored for a seasoned professional adept at establishing order amidst uncertainty and achieving results across diverse teams and domains.In this role, you will lead cross-functional programs aimed at enhancing system reliability, scalability, and operational quality. Your responsibilities include refining incident response strategies, ensuring production readiness, and innovating software testing and deployment methods. We seek a TPM with substantial technical expertise and a history of influencing system-level quality and delivery culture on a large scale.Key ResponsibilitiesOversee the Quality & Reliability Program: Articulate and implement the vision for quality, encompassing proactive practices (testing, deployment, observability), reactive processes (incident response, external communications), and cultural norms (quality ownership, readiness).Lead Cross-Functional Initiatives: Propel reliability and quality projects across Engineering, Product, Operations, and Customer Success teams.Ensure Production Readiness: Manage the Production Readiness Review (PRR) process, validating that all releases adhere to reliability standards prior to going live.Establish and Monitor SLOs: Define and track Service Level Objectives (SLOs), enhancing visibility into reliability metrics and leading initiatives to meet or exceed targets.Streamline Incident Management: Optimize incident response and postmortem processes, driving improvements in tooling, communication, and accountability.Enhance Tooling & Automation: Collaborate with teams to advance observability, alerting, testing automation, and incident response tools.Proactively Manage System Risk: Identify potential risk factors early on, develop mitigation strategies, and drive prompt resolutions.Foster Cross-Departmental Alignment: Influence Engineering, Product, Operations, and GTM teams to prioritize reliability, integrating quality into every project.Monitor Progress: Utilize tools such as Atlas, Jira, and internal dashboards to maintain clarity on objectives, risks, and outcomes.Promote Continuous Learning: Develop programs that ensure lessons are learned from every incident, test edge cases, and strengthen our systems continuously.

At d-Matrix, our mission is to unlock the transformative power of generative AI, driving the evolution of technology. We stand at the cutting edge of both software and hardware innovations, continually expanding the horizons of what is achievable. Our workplace culture is characterized by respect and collaboration.We place a high value on humility and encourage open communication. Our team is diverse, with a variety of perspectives that lead to superior solutions. We are on the lookout for individuals who are excited about overcoming challenges and are committed to delivering results. Are you ready to explore your potential? Together, we can shape the limitless possibilities of AI.Job Location:This is a hybrid role that requires you to work on-site at our Santa Clara, CA headquarters 3-5 days a week.About the Role:As a Principal Hardware Design Engineer at d-Matrix, you will play a pivotal role in our hardware organization, spearheading the development of cutting-edge platforms for our silicon-integrated AI accelerators. Your work will not merely involve designing boards; you will be laying down the physical framework that enables our Chiplet-based NPU (Neural Processing Unit) to tackle the most significant challenges in LLM inference within the industry.Key Responsibilities:Architectural Leadership: Oversee the complete hardware development lifecycle for sophisticated, high-performance AI accelerator PCIe cards and chassis platforms.Detailed Electrical Design: Manage schematic capture, component selection, and comprehensive BOM oversight for multi-rail, high-power designs.High-Speed Design: Design and supervise the layout of ultra-high-speed interfaces, such as PCIe Gen5/6, CXL, and custom chiplet-to-chiplet interconnects.Power Delivery (PDN): Develop resilient power delivery networks capable of managing high-current transients and low-voltage rails typical of advanced AI silicon.Cross-Functional Collaboration: Work closely with Silicon, Signal Integrity (SI/PI), Thermal, and Mechanical teams to ensure seamless product integration and performance.DFx & Manufacturing: Champion Design for Excellence (DFM, DFT, DFA) to guarantee high-yield production and long-term reliability in data center settings.Mentorship: Serve as a technical mentor, guiding junior engineers and establishing the standard for best practices in hardware design throughout the organization.

Join us in revolutionizing the data storage industry! As part of a dynamic and innovative team at Pure Storage, you will contribute to cutting-edge technology that reshapes the future of data solutions. Here, you'll not only lead with creativity but also grow alongside the brightest minds in the field.If you’re eager to embrace limitless opportunities and make a significant impact in the tech sphere, we invite you to be part of our journey.THE ROLEAs the Senior Technical Program Manager for Hyperscale Operations, your pivotal role will be to connect hardware engineering with global manufacturing. You will spearhead the production readiness of storage solutions integral to expansive cloud infrastructures. Your goal will be to translate intricate technical designs into scalable, high-quality products by guiding cross-functional teams through the essential stages from qualification to volume production. You will ensure that our hyperscale partners receive top-tier technology according to an aggressive global timeline.WHAT YOU’LL DOOrchestrate Global Product Launches: Oversee the comprehensive execution of hardware programs by aligning engineering milestones with manufacturing readiness, guaranteeing a smooth transition from design to mass production.Manage Strategic Partner Performance: Foster accountability with system integrators and contract manufacturers to achieve rigorous cost, quality, and scheduling goals, directly influencing the company’s capacity to satisfy hyperscale market needs.Mitigate Technical and Operational Risk: Proactively identify architectural hurdles and supply chain dependencies early in the lifecycle, implementing recovery plans to protect program timelines and product quality.Synthesize Executive Intelligence: Convert complex technical trade-offs and program health metrics into actionable insights for senior management, facilitating rapid decision-making in a dynamic, uncertain environment.Optimize Execution Frameworks: Develop and enhance cross-functional workflows and scaling tools to decrease time-to-market and enhance the predictability of large-scale hardware deployments.WHAT YOU BRINGTechnical Program Leadership: Demonstrated proficiency in navigating the complexities of hardware lifecycles—especially in storage, server, or large-scale data center environments—from initial qualification through worldwide distribution.

Role overview Arista Networks seeks a Lead Principal Optical Hardware Engineer in Santa Clara. This senior role focuses on designing and building advanced optical hardware for next-generation networking products. The position plays a key part in developing high-performance optical systems that align with Arista’s expanding product portfolio and customer requirements. What you will do Design and implement optical hardware solutions for networking equipment Collaborate with engineering teams to develop and refine optical systems Contribute to the ongoing advancement of Arista’s optical technology Ensure all solutions meet established performance and reliability standards

Job Title: Technical Program Manager Location: Santa Clara, CA Duration: 6 months Responsibilities: As a Technical Program Manager, you will be pivotal in ensuring the adherence to Agile and Scrum methodologies, providing guidance, and making critical decisions. Your role involves: Facilitating discussions and exploring alternative solutions.Collaborating with both internal and external remote teams to align statuses, address issues, manage risks, and coordinate communication effectively.Reviewing and coordinating proposed work from various teams including Professional Service firms and Co-Ops.Working closely with stakeholders and technical teams to document detailed requirements, process flows, and data sources during project initiation and planning.Preparing the Scope of Work (SOW) and other essential project initiation documents.Developing project schedules and coordinating tasks among teams.Accurately tracking project progress using project management tools.Managing the full project lifecycle including the review cycle and beyond as necessary.

Role overview Arista Networks seeks a Hardware Support Engineer based in Santa Clara. This role centers on maintaining and improving hardware systems to meet performance and reliability targets. What you will do Troubleshoot hardware issues and collaborate with other teams to resolve problems Implement solutions for technical challenges Provide technical support to clients as needed Analyze hardware performance and conduct relevant tests Create clear documentation for system improvements Impact This position plays a key role in upholding high standards for system reliability and client satisfaction at Arista Networks.

Join Our Innovative Team: At nEye.ai, we are not just another startup; we are pioneers in optical switch technology, set to transform the data center landscape. Our cutting-edge MEMS-based silicon photonics optical circuit switches (OCS) are designed to tackle critical bottlenecks in AI processing by facilitating direct optical interconnections among an extensive network of GPUs and memory units. The SuperSwitch, our flagship product, stands out with its ultra-low power consumption and high radix compact chip-scale design, delivering superior performance, efficiency, and scalability for hyperscale data centers. Position Overview: We are currently seeking a talented and detail-oriented Photonics Systems Test Engineer to spearhead the testing and characterization of our silicon photonics systems. This role is crucial for maintaining the highest quality and performance standards for our OCS product. You will apply your hands-on expertise in various optical metrics and measurement techniques while utilizing advanced testing equipment. Your responsibilities will include not only executing tests but also designing innovative testing methodologies, evaluating testing equipment, and driving test automation initiatives.

Join Arista Networks as a Senior Sustaining Hardware Engineer, where you will play a crucial role in ensuring the longevity and performance of our hardware solutions. In this position, you will collaborate with cross-functional teams to identify areas of improvement, troubleshoot hardware issues, and develop robust solutions that enhance product reliability and customer satisfaction.

Join Eataly Silicon Valley as a Host, where you will be the first point of contact for our guests, creating memorable dining experiences. As a Host, you will welcome patrons warmly, manage reservations, and ensure a smooth seating process. Your role is vital in setting the tone for the guests' dining experience, making them feel valued and at home.

Join the innovative team at d-Matrix, where we are dedicated to harnessing the power of generative AI to revolutionize technology. We are pioneers in software and hardware advancements, constantly pushing the envelope of what is feasible. Our workplace is built on a foundation of respect and collaboration.We value humility and prioritize open communication. Our inclusive team thrives on diverse perspectives, leading to superior solutions. If you're passionate about overcoming challenges and driven by results, we invite you to explore your playground with us. Together, let's unlock the endless possibilities of AI.Location: This role requires you to work onsite at our Santa Clara, CA headquarters three days a week.What You Will Do:Prepare for an exciting adventure as you engage in the bring-up, validation, and debugging of a revolutionary interference accelerator chip/chiplets! Anticipate the following responsibilities:· Lead the bring-up, validation, and debugging of cutting-edge interference accelerator chiplets, including the validation of high-speed serial protocols such as PCIe Gen5, high-speed memory interfaces like LPDDR5, and die-to-die chiplet interconnect blocks.· Innovate and implement:** Collaborate with your energetic team to develop and execute detailed test bring-up and validation plans, alongside automating randomization of software/firmware kernel functions and logging instrumentation with self-checking post processors.· Create impactful test scripts:** Design test scripts and embedded firmware functions for host systems to validate critical aspects of our high-speed interfaces, including PCIe, LPDDR, and D2D, expanding the frontiers of technology.· Equip your environment:** Work with your team to procure state-of-the-art lab equipment, ensuring you have the necessary tools for success.· Collaborate effectively:** Partner closely with hardware, software, and operations teams to tackle exciting challenges such as ATE tests and hardware/software debugging, nurturing a culture of teamwork and innovation.

Join the dynamic team at dstaff as a Program Manager, where you will play a pivotal role in driving strategic initiatives and leading cross-functional projects. This position offers an exciting opportunity to make a significant impact within the organization while collaborating with a talented group of professionals.

At Pure Storage, we are at the forefront of technological innovation, fundamentally transforming the data storage landscape. Join us and be a part of a dynamic team where your innovative ideas lead the way to success. This is more than just a job; it's an opportunity to make a significant impact in the tech industry. If you're ready to explore limitless possibilities and create a lasting legacy, we invite you to join our team.THE ROLEWe are looking for a passionate PCIe Hardware Engineer to join Pure’s Datastore team. Our company develops cutting-edge, high-performance, energy-efficient, and cost-effective storage solutions. In this role, you will play a crucial part in productizing our unique storage solutions for our clients.WHAT YOU'LL DOLead the triage, root cause analysis, and resolution of technical issues raised by internal teams, manufacturing, and Joint Development Manufacturers (JDMs), focusing on PCIe Gen5 and Gen6 interfaces, NVMe features, and SMBus.Maintain comprehensive documentation and provide regular updates to stakeholders throughout the issue resolution process.Guide the development of validation test plans for PCIe, NVMe, and SMBus, facilitating early-phase chip bring-up and regression testing during the entire development cycle.Conduct failure analysis and root cause investigations to address field issues and customer escalations efficiently.Utilize automation and AI tools, such as Augment and Glean, to enhance issue triaging and support agent development.Offer technical leadership and mentorship to junior engineers, fostering a collaborative and supportive environment.This position is primarily office-based, and you will be expected to work from the Santa Clara office in accordance with Pure Storage's policies, except during approved leave or travel.