About the job
At Efficient, we are revolutionizing the computing landscape with our cutting-edge, energy-efficient general-purpose processor. Our groundbreaking technology consumes 100 times less energy than the leading ultra-low-power processors available today, while remaining compatible with standard high-level programming languages and AI/ML frameworks. This exceptional efficiency allows for continuous AI/ML operation on a single AA battery for 5 to 10 years, making it easier than ever to harness the power of IoT devices for capturing and curating first-party data that will drive the next computing revolution.
We are on the lookout for a CAD Lead - Physical Design Flows and Infrastructure to join our innovative hardware engineering team. This unique opportunity allows you to establish CAD flows and infrastructure from the ground up, shaping the future of our physical design methodologies.
As a pivotal member of our newly formed hardware engineering group, you will play a critical role in transitioning our products from initial development stages to market launch and high-volume production. Join us in redefining the future of edge computing!
Key Responsibilities
- Develop and drive physical design flows and methodologies for advanced FinFET and multi-patterning technologies using Cadence Tempus or Synopsys Primetime.
- Create repeatable, predictable design processes that are agnostic to specific designs and methodologies.
- Build infrastructure that enables consistent, rapid design under tight timelines for a diverse range of product lines in the energy-efficient edge AI computing sector.
- Collaborate closely with physical design team leads to establish comprehensive build and signoff flows.
- Develop regression frameworks to ensure high-quality flows, allowing engineers to devote over 90% of their time to design tasks rather than tool management.
- Create quality-checking utilities to enhance design efficiency.
- Implement a unified environment for managing all collateral specifications (standard cells, memory, PDK, hard IPs) and flow dependencies (cycle time, PVTRC corners, design configurations).
- Coordinate with third-party vendor resources to optimize workflow.
- Pursue continuous improvements in flow consistency and efficiency across multiple product lines.

