Integration and Verification Engineer, Turbogenerator

About Archer Aviation Archer Aviation designs and builds all-electric vertical takeoff and landing (eVTOL) aircraft in San Jose, California. The company focuses on sustainable air mobility, aiming to move four passengers quietly and with minimal environmental impact. The team values ambitious problem-solving and believes that a diverse, inclusive workplace is essential for innovation and success. Every team member’s perspective contributes to the company’s progress. Role Overview: Integration and Verification Engineer, Turbogenerator This engineer leads the verification of integrated hybrid powertrain systems, with a focus on the turboshaft/turbogenerator powertrain and its related components. Main Responsibilities Direct the verification process for integrated hybrid powertrain systems. Apply systems engineering methods to validate the turboshaft/turbogenerator powertrain, including batteries, motors, and complex mechanical parts. Manage verification activities during both bench testing and aircraft integration, including the start of flight test campaigns. Offer technical input in design reviews, especially regarding testing and operational needs for the turbogenerator. Work closely with suppliers, engineers, and other stakeholders to keep verification activities safe and on schedule. Monitor third-party stakeholders to ensure they meet deadlines and uphold safety standards.

Archer, based in San Jose, California, develops all-electric vertical takeoff and landing aircraft designed for four passengers. The company is dedicated to advancing sustainable air mobility and reducing noise pollution through innovative aerospace solutions. Archer values ambitious goals and supports a diverse, inclusive workplace where every team member is respected. Role overview The Powertrain Platform Verification Engineer ensures the reliability and safety of critical platform software used in Archer’s aircraft. This position focuses on thorough testing and validation in line with industry certification standards, especially DO-178C. Main responsibilities Verify and validate safety-critical platform software components according to DO-178C standards. Design and document detailed test plans, test cases, and procedures based on software requirements. Execute Software-in-the-Loop (SIL) and Hardware-in-the-Loop (HIL) tests to evaluate platform software algorithms and low-level drivers. Identify and track software defects using automated systems, collaborating with embedded developers to analyze root causes and verify fixes. Develop and maintain automated test scripts and frameworks in C/C++ and Python to enhance testing efficiency. Create and execute tests for software fault detection and diagnostic algorithms, covering a range of system faults and anomalies. Take part in software audits and reviews to ensure compliance with DO-178C certification requirements.

Archer Aviation, an innovative aerospace firm headquartered in San Jose, California, is on a mission to revolutionize air travel with our all-electric vertical takeoff and landing aircraft. Our commitment to sustainable air mobility drives us to design, manufacture, and operate an aircraft capable of carrying four passengers while minimizing noise pollution.We are passionate about addressing complex challenges and believe that a diverse workforce enhances our problem-solving capabilities, leading to superior insights and success. We strive to foster an equitable and inclusive workplace that celebrates the unique contributions of every team member.Key Responsibilities:Conduct verification and validation of safety-critical software components for the aircraft battery management system (BMS) in alignment with DO-178C standards.Develop and document detailed test plans, cases, and procedures based on software requirements.Perform Software-in-the-Loop (SIL) and Hardware-in-the-Loop (HIL) testing to validate battery algorithms and drivers.Identify, document, and manage software defects using automated tracking systems; collaborate with development teams to analyze root causes and validate resolutions.Create and uphold automated test scripts and frameworks (C/C++, Python) to optimize testing efficiency and coverage.Design and implement tests for verifying software fault detection and diagnostic algorithms, including insulation breakdown, short circuits, and sensor failures.Analyze sensor data (cell voltages, pack current) and test outcomes to ensure accurate state estimation and protective function performance.Engage in software audits and reviews to ensure compliance with DO-178C certification requirements.

Join Our Team at EtchedAt Etched, we are pioneering the development of the first AI inference system specifically designed for transformers, achieving over 10x the performance and significantly lower costs and latency compared to traditional solutions like the B200. Our custom ASICs empower the creation of groundbreaking products, such as real-time video generation models and highly advanced reasoning agents. Backed by substantial investments from leading venture capitalists and a team of top engineers, we are reshaping the foundational technology of one of the fastest-growing industries in history.Role OverviewWe are looking for a talented Design Verification Engineer to become a vital part of our Systems/Performance Verification team. In this role, you will be responsible for ensuring that the custom IPs driving our innovative Sohu architecture—such as systolic arrays, DMA engines, and Network on Chip (NoC)—are reliable, high-performing, and ready for silicon implementation. This position requires innovative thinking, robust technical skills, and a passion for solving intricate verification challenges. You will collaborate closely with architects, RTL designers, and software/firmware/emulation teams to validate the accuracy and performance of our hardware-software integration.Key ResponsibilitiesCollaborate with architects and RTL designers to verify the performance features of the design and ensure alignment with performance models, both pre- and post-silicon.Partner with software and application developers to identify performance bottlenecks and optimize software solutions.Create comprehensive test plans and develop test infrastructure/tools aimed at performance tuning, correlation, and verification.Enhance and maintain architectural performance models.Design tests in SystemVerilog, Python, or other vectors to debug and correlate RTL with performance models.Develop SystemVerilog or Python-based checkers to validate performance features.Implement coverage monitors and perform coverage analysis to ensure comprehensive testing of all performance features.Investigate performance issues and execute performance tuning on silicon.Lead end-to-end performance tuning to guarantee optimal hardware utilization, software efficiency, and architectural coherence throughout the ASIC design lifecycle.

At Archer, we are pioneering the future of sustainable air mobility with our innovative all-electric vertical takeoff and landing aircraft, designed to transport four passengers quietly and efficiently. Headquartered in San Jose, California, we are on a mission to revolutionize urban transportation while minimizing our environmental footprint.We are committed to fostering a diverse and inclusive workplace that empowers every team member. Our belief is that varied perspectives ignite creativity, enhance insights, and drive our collective success. Join us as we work together to achieve remarkable things.What You'll Do:As a Staff BMS Hardware Verification Engineer, you will take the lead in the comprehensive verification and validation of Archer’s cutting-edge Battery Management System (BMS) electronics. Your role will ensure that our hardware, sensing, and control circuits fulfill the rigorous safety, reliability, and certification standards essential for eVTOL aircraft. You will create and implement hardware verification plans, design and automate test environments, conduct environmental and functional assessments, and compile certification evidence demonstrating compliance with FAA and industry standards such as DO-160G, DO-254, and ARP4754A. Your contributions will be vital to the certification and safe operation of our battery systems, which are integral to the next generation of urban air mobility.Lead the verification and validation (V&V) processes for the Battery Management System (BMS) electronics utilized in Archer’s high-voltage battery packs.Create detailed hardware verification plans, test procedures, and traceability matrices that align with system and certification requirements (DO-160G, DO-254, ARP4754A).Establish test methodologies for environmental, functional, and safety verification of BMS printed circuit board assemblies (PCBAs) and associated sensing electronics.Collaborate with systems, design, and certification engineering teams to extract verification requirements from system design documentation and certification plans.Design, construct, and automate hardware test setups, including instrumentation, data acquisition systems, power supplies, CAN interfaces, and fault-injection mechanisms.Execute and document test campaigns at the component, subsystem, and integrated aircraft levels to validate compliance with FAA airworthiness standards.Generate comprehensive test reports and assist with certification deliverables, including compliance matrices and traceability documentation.

At Efficient Computer, we are at the forefront of technological innovation, developing the world's most energy-efficient general-purpose computer processor. Our groundbreaking patented technology consumes 100 times less energy than currently available ultra-low-power processors, all while being programmable with high-level programming languages and AI/ML frameworks. This exceptional efficiency allows for continuous AI/ML operation on a single AA battery for 5-10 years. Our platform's unique capabilities empower IoT devices to intelligently gather and manage first-party data, paving the way for the next computing revolution.We invite skilled and passionate professionals to join us as a Lead Digital Verification Engineer. In this pivotal role, you will spearhead the functional verification of complex SoC/IP designs from specification to tapeout within our newly established hardware engineering team. You will be responsible for defining verification strategies, establishing methodology standards, building and mentoring a team of verification engineers, and ensuring quality and readiness for sign-off. This position requires a robust understanding of modern verification methodologies (UVM, embedded C, and compiler-generated trace-driven testing) and exceptional leadership skills to drive success across multi-block chip programs on schedule. Your contributions will be crucial in refining our internal processes for creating reliable and verified designs, including our upcoming product line that aims to enhance computing performance while optimizing energy efficiency.This is a rare opportunity to influence our development processes and products as we transition from initial development stages to market launch and large-scale production. Join us and help shape the future of computing at the edge and beyond!

About UsAt chipstack, we are revolutionizing the way chips are designed in an era where the complexity and demands of technology are constantly evolving. Our team combines expertise from top-tier companies such as Qualcomm, Nvidia, Google, and Meta, and we are passionate about integrating artificial intelligence into the Electronic Design Automation (EDA) landscape.Backed by leading investors like Khosla Ventures and Cerberus, we are already working with over 10 pioneering customers, ranging from Fortune 100 companies to innovative AI silicon startups. Join us as we drive the future of chip design.Position OverviewWe are on the lookout for a motivated Functional Verification Engineer with a strong background in UVM test bench development. Your role will be pivotal in harnessing AI to transform traditional verification methodologies, ensuring the design and validation of cutting-edge semiconductor technologies. Collaborating with a talented team of machine learning and software engineers, you will utilize advanced AI tools to innovate our verification processes.Key Responsibilities• Drive the application of machine learning to enhance pre-silicon functional verification methodologies including UVM.• Utilize AI-powered EDA tools to streamline design and verification workflows.• Identify challenges within UVM verification and implement AI-driven solutions.• Collaborate with customers to understand their needs and provide groundbreaking verification strategies.• Work closely with machine learning and software engineering teams to ensure high-quality outputs.• Stay updated on the latest advancements in AI-powered hardware verification and contribute to internal knowledge sharing.Required Qualifications• Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.• A minimum of 3 years of experience in digital design and verification, with a strong emphasis on UVM.

About Etched Etched builds the first AI inference system tailored for transformers. The company’s custom ASICs deliver over 10x the performance of standard solutions, with lower costs and latency than a B200. These chips enable products like real-time video generation models and advanced reasoning agents. Etched is backed by major investors and staffed by engineers focused on reshaping AI infrastructure. Role Overview: Design Verification Engineer - SoC This San Jose-based role sits within the Systems and Performance Verification team. The Design Verification Engineer ensures Etched’s custom IPs, including systolic arrays, DMA engines, and NoCs, are ready for silicon. The work spans verifying performance, collaborating with architects and designers, and supporting the entire hardware-software stack. Expect to tackle complex verification challenges alongside colleagues in architecture, RTL, and software/firmware. What You Will Do Work with architects and RTL designers to verify performance features against models, both before and after silicon. Collaborate with software teams to spot and resolve performance bottlenecks. Create test plans and develop tools for performance tuning, correlation, and verification. Maintain and improve architectural performance models. Write tests in SystemVerilog, Python, or vectors to debug and align RTL with performance models. Develop checkers in SystemVerilog or Python to verify performance features. Implement coverage monitors and analyze results to ensure thorough testing. Investigate and tune performance issues on silicon. Lead end-to-end performance tuning to optimize hardware use, software efficiency, and architectural fit across the ASIC design lifecycle. What Makes a Strong Candidate Understanding of digital design, RTL, and ASIC design flows. Hands-on experience with performance verification tools and methodologies. Strong analytical and problem-solving abilities. Comfort working on several projects at once and adapting to shifting priorities.

About EtchedEtched is at the forefront of innovation, developing the world’s first AI inference system specifically designed for transformers. Our technology outperforms traditional GPUs with over 10x greater performance, significantly reducing cost and latency compared to existing solutions. With Etched ASICs, we're enabling the creation of groundbreaking products, such as real-time video generation models and highly complex reasoning agents. Our team, comprised of top engineers, is supported by substantial investments from leading investors, and we are redefining the infrastructure for the rapidly evolving AI industry.Job SummaryWe are looking for a passionate Design Verification Engineer to join our Internal IP DV team. In this role, you will be responsible for ensuring that the custom IPs that drive Sohu—such as systolic arrays, DMA engines, and NoCs—are robust, high-performance, and ready for silicon implementation. This position requires both creativity and deep technical expertise to address complex verification challenges. You will work in collaboration with architects, RTL designers, and software/firmware/emulation teams to validate correctness and performance across the entire hardware-software stack.Key ResponsibilitiesDesign, develop, and maintain UVM/SystemVerilog testbenches for high-performance IPs including compute arrays, DMAs, NoCs, and memory subsystems.Create and implement comprehensive verification plans that address functional correctness, corner cases, concurrency issues, and performance bottlenecks.Troubleshoot complex datapath and protocol issues within RTL and testbench environments.Collaborate closely with architects and designers to confirm functionality and design intent.Engage with software, firmware, and emulation teams to ensure thorough end-to-end bring-up and debugging coverage.Contribute to the development of reusable DV infrastructure, coverage models, and improvements in methodology.QualificationsYou may be an ideal candidate if you possess the following qualifications:Expertise in UVM and SystemVerilog.Exceptional debugging and problem-solving skills related to complex digital designs.In-depth knowledge of computer architecture and the fundamentals of digital design.Hands-on experience in verifying datapaths, memory systems, interconnects, or high-throughput fabrics.

About EtchedEtched is pioneering the world’s first AI inference system specifically designed for transformers, achieving over 10 times greater performance and significantly reduced costs and latency compared to traditional solutions like B200. Our ASICs enable the development of products that were previously unattainable with GPUs, including real-time video generation models and highly advanced parallel reasoning agents. With substantial backing from leading investors and a team of exceptional engineers, Etched is transforming the infrastructure landscape for one of the fastest-growing industries.Job SummaryWe are on the lookout for a talented Design Verification Engineer to join our Interface IP DV team. In this role, you will collaborate with architects, designers, and vendors to ensure that all architectural requirements are flawlessly integrated into the IP subsystems and interfaces we are developing. You will validate the correctness and performance across the entire hardware-software stack. This position requires creativity, strong technical skills, and a passion for overcoming complex verification challenges.Key ResponsibilitiesTake complete ownership of one or more IP subsystems, including PCIe, Ethernet, CPU (ARC/ARM), low-power peripherals, and sensors.Comprehend vendor IP configurations and facilitate communication with the internal IP team.Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.Collaborate with integration and SoC DV teams to ensure the seamless operation of external IPs within the overall chip architecture.Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring thorough verification across corner cases and stress scenarios.

Job Title: Principal Engineer, Signal Integrity and Power IntegrityOffice Location: San Jose, CAWork Model: OnsiteAbout SK hynix AmericaAt SK hynix America, we are pioneers in semiconductor innovation, leading the development of advanced memory solutions that power a wide array of devices, from smartphones to data centers. As a global frontrunner in DRAM and NAND flash technologies, we are driving the evolution of mobile technology, enhancing cloud computing capabilities, and exploring future technologies. Our state-of-the-art memory technologies are crucial for the most advanced electronic devices and IT infrastructures, providing improved performance and superior user experiences across the digital realm.We invite visionary minds to join our mission of shaping the future of technology. Here at SK hynix America, you will collaborate with a team dedicated to pioneering advanced memory solutions while upholding a strong commitment to sustainability. We are not merely responding to technological advancements; we are leading them through significant investments in artificial intelligence, machine learning, and environmentally friendly practices. As we expand our market influence and redefine the boundaries of semiconductor technology, we welcome you to be a part of our journey in creating the next generation of memory solutions that will shape the future of computing.Job Summary:SK hynix America is on the lookout for a Principal Engineer to spearhead the Signal Integrity and Power Integrity (SIPI) strategy for cutting-edge advanced packaging technologies. In this role, you will be responsible for the design, analysis, and validation of next-generation advanced packaging solutions for HBM and beyond, including logic-memory integration. This position requires extensive technical expertise in high-speed interface design, collaboration with global R&D teams, and contributions to industry standards for advanced packaging.Responsibilities:Strategic Leadership: Define and manage the SIPI roadmap for advanced packaging families, ensuring alignment of technical direction with product and business objectives.Architecture & Design: Lead the development of high-performance SiP architectures (HBM, interposer, 3D stacks) and validate power delivery and signal integrity throughout the entire stack—from silicon to substrate.Methodology Development: Innovate and disseminate best-practice SIPI methodologies, including electromagnetic extraction, multi-port S-parameter modeling, and power-network analysis for complex packaging environments.Technical Ownership: Supervise the complete design flow (package definition, simulation, and validation).

AppZen stands at the forefront of autonomous spend-to-pay software, leveraging patented artificial intelligence to meticulously process data from thousands of sources. Our innovative solutions empower organizations to gain comprehensive insights into enterprise spending, facilitating more informed business decisions. By integrating seamlessly with existing accounts payable, expense, and card workflows, AppZen transforms data into actionable insights, ensuring rapid processing and minimizing instances of fraud and unnecessary expenditures. Trusted by global enterprises, including one-third of the Fortune 500, our invoice, expense, and card transaction solutions replace manual finance processes, enhancing the speed and agility of businesses worldwide. Discover more at www.appzen.com.As an Integration Engineer at AppZen, you will play a pivotal role in designing, implementing, and maintaining integrations between our platform and client enterprise systems. This hands-on technical position demands a focus on delivering robust and scalable integration solutions. You will collaborate closely with customer technical teams, craft code, configure iPaaS platforms, troubleshoot production issues, and ensure seamless data flow across systems. If you thrive on solving intricate integration challenges and take pride in the direct impact of your work on customer success, this is the ideal role for you.

About UsAt Chipstack, we recognize that chips are the backbone of modern technology, yet the design processes have not evolved significantly over the decades. The rising complexity and specialization needed to meet performance demands from AI applications drive our mission to innovate the chip design landscape.Our agile and technically adept team is composed of experts with backgrounds in esteemed companies like Qualcomm, Nvidia, Google, Meta, and the Allen Institute for AI. We’re supported by prominent investors such as Khosla Ventures, Cerberus, and Clear Ventures, and we have successfully partnered with over 10 pioneering customers, ranging from Fortune 100 firms to revolutionary AI silicon startups.About This RoleWe are on the lookout for a skilled Formal Verification Engineer to become a vital part of our innovative team. The ideal candidate will possess extensive experience in all areas of Formal Verification, including SVA, Property Verification, Formal Methods/Abstractions, and Methodology, along with scripting proficiency. In this role, you will contribute to the development of Chipstack’s groundbreaking Formal Verification Agent, playing a crucial part in enhancing the quality and capabilities of our tools.You will collaborate closely with seasoned chip designers who have crafted intricate chips, machine learning scientists who have scaled LLM training, and exceptional infrastructure and software engineers. Your expertise in Formal Verification will be instrumental in creating the next generation of AI-integrated verification tools.

About EtchedAt Etched, we're pioneering the world's first AI inference system uniquely designed for transformers, offering over 10 times the performance with significantly reduced costs and latency compared to B200 systems. Our custom ASICs empower the development of groundbreaking products, including real-time video generation models and highly sophisticated deep reasoning agents. With substantial backing from top-tier investors and a team of exceptional engineers, we are revolutionizing the infrastructure layer essential for today's rapidly evolving industry.Job SummaryWe are on the lookout for a talented Rack Level Integration Engineer to take a pivotal role in the qualification and integration of various components within our data center racks. In this position, you will manage the rack-level integration for our Sohu system product, which includes top-of-rack (ToR) switches, advanced water cooling systems, Coolant Distribution Units (CDUs), heat exchangers, and rack management functionalities. Your responsibilities will include hands-on lab work for racking and stacking, setting up high-touch rack configurations, and ensuring optimal performance, reliability, and readiness for deployment.Key ResponsibilitiesIntegrate and configure all components within a data center rack, including servers, storage systems, networking equipment, power solutions, and cooling systems.Configure and integrate top-of-rack switches for effective rack operation.Manage and integrate high-power water cooling systems, including CDUs and heat exchangers.Set up, test, and qualify comprehensive rack solutions to ensure they meet performance, reliability, and efficiency standards.Integrate and configure smart PDUs to facilitate efficient power distribution and ensure compatibility with rack-level power management.Maintain a thorough understanding of rack-level management functions, including monitoring, control, and automation of components.Perform hands-on lab racking and stacking, including the assembly and setup of intricate rack configurations.Create and sustain detailed documentation for rack-level integrations, covering specifications, installation procedures, test results, and issue tracking.Collaborate closely with cross-functional teams including mechanical engineers, systems engineers, vendors, and integrators to ensure seamless operation at the rack level.Regularly engage with contract manufacturers in Taiwan, both remotely and on-site.

About EtchedEtched is pioneering the development of the globe's first AI inference system uniquely designed for transformers, achieving over tenfold improvements in performance while significantly reducing cost and latency compared to traditional systems like the B200. With Etched ASICs, you can create groundbreaking products previously deemed impossible with GPUs, including real-time video generation models and highly intricate chain-of-thought reasoning agents. Supported by substantial investment from premier investors and a team of top engineers, Etched is revolutionizing the foundational infrastructure for the fastest-expanding industry in history.Job SummaryAs a Design Verification Intern, you will play a critical role in ensuring the reliability and performance of our custom IPs that drive our chips, including systolic arrays, DMA engines, and NoCs. This position requires innovation, strong technical skills, and a proactive approach to complex verification challenges. You will work closely with architects, RTL designers, and software/firmware/emulation teams to validate the correctness and performance across the entire hardware-software stack.QualificationsCurrently pursuing a Bachelor’s, Master’s, or PhD in electrical engineering, computer engineering, or a relevant field.Knowledge of high-speed digital logic.Familiarity with ASIC or SoC design principles.Experience with SystemVerilog, UVM, or Python.Understanding of verification processes and test bench development.Acquainted with physical design flows and related tools.Eager to quickly learn about transformers and various aspects of modern artificial intelligence.Preferred QualificationsExperience with transformer models and machine learning.Familiarity with UVM or formal verification techniques.Proficiency in Python or similar scripting languages.We encourage all candidates to apply, even if they do not meet every single qualification.Program Details12-week paid internship running from June to August 2026.Generous housing assistance for those relocating.

We are seeking a dedicated and detail-oriented System Verification Specialist II to join our dynamic team at bcforward. In this role, you will be responsible for developing and executing verification strategies to ensure the quality and reliability of our systems. Your expertise will contribute significantly to our mission of delivering top-notch solutions to our clients.

We are seeking a talented Power Integrity Engineer to join our innovative team at Lumilens in San Jose, California. In this role, you will be responsible for ensuring the integrity of power systems within silicon components, contributing to the advancement of our cutting-edge technology.As a Power Integrity Engineer, you will work closely with cross-functional teams to analyze and optimize power distribution networks, develop simulations, and conduct testing to ensure product reliability. Your expertise will play a crucial role in delivering high-performance solutions that meet our clients' needs.

Axiado is looking for a System Engineer focused on Platform Integration in San Jose. This position centers on designing and implementing integrated systems that support the company's technology solutions. Role overview The System Engineer will work closely with teams across multiple functions to ensure that platforms connect smoothly and perform reliably. The work involves both planning and hands-on implementation of integration strategies. What you will do Design integrated systems that support Axiado's technology products Implement solutions to connect platforms effectively Collaborate with other teams to maintain seamless integration and system performance Collaboration This role requires ongoing communication with engineering, product, and other departments to deliver integrated solutions that meet company objectives.

Location: On-site in San Jose, California or Trondheim, NorwayAbout UsBacked by leading venture capitalists in Silicon Valley, Trener Robotics is at the forefront of revolutionizing robotics. Our approach merges cutting-edge AI for intuitive programming with pre-trained skill models, ensuring expertise in industrial tasks. With offices in San Jose (USA) and Trondheim (Norway), our software empowers users with exceptional ease of use and unparalleled capabilities, enabling robots to think, adapt, and execute complex tasks efficiently.About the RoleWe are on the lookout for a dedicated Software-Focused Integration Engineer to join our dynamic robotics team. In this pivotal position, you will enhance and deploy the software architecture that drives our robotic systems. Your primary responsibilities will include integrating sensors, peripherals, and control systems through robust software solutions, facilitating seamless communication between hardware components and our AI-driven robotics platform.Key ResponsibilitiesDesign and implement software integration strategies for robotic systems, including sensor suites, cameras, and peripheral devices.Develop and maintain drivers and interfaces for various peripherals such as machine tools, conveyor systems, sensors, and PLCs.Integrate and calibrate vision systems into robotic workflows.Set up robot workcells and conduct rigorous software validation testing.Review robot scripts to ensure proper functionality.Provide comprehensive technical documentation and support for software integration processes.Diagnose and resolve software integration issues and performance challenges.

Archer Aviation Inc. is pioneering the future of sustainable air travel with our innovative all-electric vertical takeoff and landing (eVTOL) aircraft. Based in San Jose, California, our mission is to enhance air mobility while minimizing noise and environmental impact. We are dedicated to designing, manufacturing, and operating an aircraft that can transport four passengers with unparalleled efficiency.At Archer, we embrace challenges and aspire to achieve greatness. We believe that a diverse workplace fosters intelligence and creativity, leading to better outcomes for everyone. We are committed to creating an inclusive culture that values our differences and supports the success of every team member.Key Responsibilities:Lead the design and optimization of environmental control systems for eVTOL aircraft, ensuring exceptional thermal and mechanical performance.Collaborate effectively with cross-functional teams, including mechanical, aerospace, electrical, and software engineers, to ensure seamless system integration and aircraft-level optimization.Develop comprehensive system requirements and verification procedures, supporting certification documentation to comply with aviation standards.Manage ECS development, integration, and verification activities, coordinating with both internal teams and external suppliers.