Functional Verification Engineer - Leveraging AI for Chip Design

About UsAt chipstack, we are revolutionizing the way chips are designed in an era where the complexity and demands of technology are constantly evolving. Our team combines expertise from top-tier companies such as Qualcomm, Nvidia, Google, and Meta, and we are passionate about integrating artificial intelligence into the Electronic Design Automation (EDA) landscape.Backed by leading investors like Khosla Ventures and Cerberus, we are already working with over 10 pioneering customers, ranging from Fortune 100 companies to innovative AI silicon startups. Join us as we drive the future of chip design.Position OverviewWe are on the lookout for a motivated Functional Verification Engineer with a strong background in UVM test bench development. Your role will be pivotal in harnessing AI to transform traditional verification methodologies, ensuring the design and validation of cutting-edge semiconductor technologies. Collaborating with a talented team of machine learning and software engineers, you will utilize advanced AI tools to innovate our verification processes.Key Responsibilities• Drive the application of machine learning to enhance pre-silicon functional verification methodologies including UVM.• Utilize AI-powered EDA tools to streamline design and verification workflows.• Identify challenges within UVM verification and implement AI-driven solutions.• Collaborate with customers to understand their needs and provide groundbreaking verification strategies.• Work closely with machine learning and software engineering teams to ensure high-quality outputs.• Stay updated on the latest advancements in AI-powered hardware verification and contribute to internal knowledge sharing.Required Qualifications• Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.• A minimum of 3 years of experience in digital design and verification, with a strong emphasis on UVM.

About UsAt Chipstack, we recognize that chips are the backbone of modern technology, yet the design processes have not evolved significantly over the decades. The rising complexity and specialization needed to meet performance demands from AI applications drive our mission to innovate the chip design landscape.Our agile and technically adept team is composed of experts with backgrounds in esteemed companies like Qualcomm, Nvidia, Google, Meta, and the Allen Institute for AI. We’re supported by prominent investors such as Khosla Ventures, Cerberus, and Clear Ventures, and we have successfully partnered with over 10 pioneering customers, ranging from Fortune 100 firms to revolutionary AI silicon startups.About This RoleWe are on the lookout for a skilled Formal Verification Engineer to become a vital part of our innovative team. The ideal candidate will possess extensive experience in all areas of Formal Verification, including SVA, Property Verification, Formal Methods/Abstractions, and Methodology, along with scripting proficiency. In this role, you will contribute to the development of Chipstack’s groundbreaking Formal Verification Agent, playing a crucial part in enhancing the quality and capabilities of our tools.You will collaborate closely with seasoned chip designers who have crafted intricate chips, machine learning scientists who have scaled LLM training, and exceptional infrastructure and software engineers. Your expertise in Formal Verification will be instrumental in creating the next generation of AI-integrated verification tools.

Join the innovative team at Western Digital as a Memory Chip Design Engineer. In this role, you will be at the forefront of designing and optimizing memory chip technologies that power the next generation of computing solutions. You will collaborate with cross-functional teams to drive product development from concept to production.Your contributions will directly impact the performance and efficiency of storage devices used worldwide. If you are passionate about technology and eager to push the boundaries of memory solutions, we want to hear from you!

Join Our Team at EtchedAt Etched, we are pioneering the development of the first AI inference system specifically designed for transformers, achieving over 10x the performance and significantly lower costs and latency compared to traditional solutions like the B200. Our custom ASICs empower the creation of groundbreaking products, such as real-time video generation models and highly advanced reasoning agents. Backed by substantial investments from leading venture capitalists and a team of top engineers, we are reshaping the foundational technology of one of the fastest-growing industries in history.Role OverviewWe are looking for a talented Design Verification Engineer to become a vital part of our Systems/Performance Verification team. In this role, you will be responsible for ensuring that the custom IPs driving our innovative Sohu architecture—such as systolic arrays, DMA engines, and Network on Chip (NoC)—are reliable, high-performing, and ready for silicon implementation. This position requires innovative thinking, robust technical skills, and a passion for solving intricate verification challenges. You will collaborate closely with architects, RTL designers, and software/firmware/emulation teams to validate the accuracy and performance of our hardware-software integration.Key ResponsibilitiesCollaborate with architects and RTL designers to verify the performance features of the design and ensure alignment with performance models, both pre- and post-silicon.Partner with software and application developers to identify performance bottlenecks and optimize software solutions.Create comprehensive test plans and develop test infrastructure/tools aimed at performance tuning, correlation, and verification.Enhance and maintain architectural performance models.Design tests in SystemVerilog, Python, or other vectors to debug and correlate RTL with performance models.Develop SystemVerilog or Python-based checkers to validate performance features.Implement coverage monitors and perform coverage analysis to ensure comprehensive testing of all performance features.Investigate performance issues and execute performance tuning on silicon.Lead end-to-end performance tuning to guarantee optimal hardware utilization, software efficiency, and architectural coherence throughout the ASIC design lifecycle.

About EtchedEtched is at the forefront of innovation, developing the world’s first AI inference system specifically designed for transformers. Our technology outperforms traditional GPUs with over 10x greater performance, significantly reducing cost and latency compared to existing solutions. With Etched ASICs, we're enabling the creation of groundbreaking products, such as real-time video generation models and highly complex reasoning agents. Our team, comprised of top engineers, is supported by substantial investments from leading investors, and we are redefining the infrastructure for the rapidly evolving AI industry.Job SummaryWe are looking for a passionate Design Verification Engineer to join our Internal IP DV team. In this role, you will be responsible for ensuring that the custom IPs that drive Sohu—such as systolic arrays, DMA engines, and NoCs—are robust, high-performance, and ready for silicon implementation. This position requires both creativity and deep technical expertise to address complex verification challenges. You will work in collaboration with architects, RTL designers, and software/firmware/emulation teams to validate correctness and performance across the entire hardware-software stack.Key ResponsibilitiesDesign, develop, and maintain UVM/SystemVerilog testbenches for high-performance IPs including compute arrays, DMAs, NoCs, and memory subsystems.Create and implement comprehensive verification plans that address functional correctness, corner cases, concurrency issues, and performance bottlenecks.Troubleshoot complex datapath and protocol issues within RTL and testbench environments.Collaborate closely with architects and designers to confirm functionality and design intent.Engage with software, firmware, and emulation teams to ensure thorough end-to-end bring-up and debugging coverage.Contribute to the development of reusable DV infrastructure, coverage models, and improvements in methodology.QualificationsYou may be an ideal candidate if you possess the following qualifications:Expertise in UVM and SystemVerilog.Exceptional debugging and problem-solving skills related to complex digital designs.In-depth knowledge of computer architecture and the fundamentals of digital design.Hands-on experience in verifying datapaths, memory systems, interconnects, or high-throughput fabrics.

About EtchedEtched is pioneering the development of the globe's first AI inference system uniquely designed for transformers, achieving over tenfold improvements in performance while significantly reducing cost and latency compared to traditional systems like the B200. With Etched ASICs, you can create groundbreaking products previously deemed impossible with GPUs, including real-time video generation models and highly intricate chain-of-thought reasoning agents. Supported by substantial investment from premier investors and a team of top engineers, Etched is revolutionizing the foundational infrastructure for the fastest-expanding industry in history.Job SummaryAs a Design Verification Intern, you will play a critical role in ensuring the reliability and performance of our custom IPs that drive our chips, including systolic arrays, DMA engines, and NoCs. This position requires innovation, strong technical skills, and a proactive approach to complex verification challenges. You will work closely with architects, RTL designers, and software/firmware/emulation teams to validate the correctness and performance across the entire hardware-software stack.QualificationsCurrently pursuing a Bachelor’s, Master’s, or PhD in electrical engineering, computer engineering, or a relevant field.Knowledge of high-speed digital logic.Familiarity with ASIC or SoC design principles.Experience with SystemVerilog, UVM, or Python.Understanding of verification processes and test bench development.Acquainted with physical design flows and related tools.Eager to quickly learn about transformers and various aspects of modern artificial intelligence.Preferred QualificationsExperience with transformer models and machine learning.Familiarity with UVM or formal verification techniques.Proficiency in Python or similar scripting languages.We encourage all candidates to apply, even if they do not meet every single qualification.Program Details12-week paid internship running from June to August 2026.Generous housing assistance for those relocating.

About EtchedEtched is pioneering the world’s first AI inference system specifically designed for transformers, achieving over 10 times greater performance and significantly reduced costs and latency compared to traditional solutions like B200. Our ASICs enable the development of products that were previously unattainable with GPUs, including real-time video generation models and highly advanced parallel reasoning agents. With substantial backing from leading investors and a team of exceptional engineers, Etched is transforming the infrastructure landscape for one of the fastest-growing industries.Job SummaryWe are on the lookout for a talented Design Verification Engineer to join our Interface IP DV team. In this role, you will collaborate with architects, designers, and vendors to ensure that all architectural requirements are flawlessly integrated into the IP subsystems and interfaces we are developing. You will validate the correctness and performance across the entire hardware-software stack. This position requires creativity, strong technical skills, and a passion for overcoming complex verification challenges.Key ResponsibilitiesTake complete ownership of one or more IP subsystems, including PCIe, Ethernet, CPU (ARC/ARM), low-power peripherals, and sensors.Comprehend vendor IP configurations and facilitate communication with the internal IP team.Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.Collaborate with integration and SoC DV teams to ensure the seamless operation of external IPs within the overall chip architecture.Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring thorough verification across corner cases and stress scenarios.

About Etched Etched builds the first AI inference system tailored for transformers. The company’s custom ASICs deliver over 10x the performance of standard solutions, with lower costs and latency than a B200. These chips enable products like real-time video generation models and advanced reasoning agents. Etched is backed by major investors and staffed by engineers focused on reshaping AI infrastructure. Role Overview: Design Verification Engineer - SoC This San Jose-based role sits within the Systems and Performance Verification team. The Design Verification Engineer ensures Etched’s custom IPs, including systolic arrays, DMA engines, and NoCs, are ready for silicon. The work spans verifying performance, collaborating with architects and designers, and supporting the entire hardware-software stack. Expect to tackle complex verification challenges alongside colleagues in architecture, RTL, and software/firmware. What You Will Do Work with architects and RTL designers to verify performance features against models, both before and after silicon. Collaborate with software teams to spot and resolve performance bottlenecks. Create test plans and develop tools for performance tuning, correlation, and verification. Maintain and improve architectural performance models. Write tests in SystemVerilog, Python, or vectors to debug and align RTL with performance models. Develop checkers in SystemVerilog or Python to verify performance features. Implement coverage monitors and analyze results to ensure thorough testing. Investigate and tune performance issues on silicon. Lead end-to-end performance tuning to optimize hardware use, software efficiency, and architectural fit across the ASIC design lifecycle. What Makes a Strong Candidate Understanding of digital design, RTL, and ASIC design flows. Hands-on experience with performance verification tools and methodologies. Strong analytical and problem-solving abilities. Comfort working on several projects at once and adapting to shifting priorities.

At Efficient Computer, we are at the forefront of technological innovation, developing the world's most energy-efficient general-purpose computer processor. Our groundbreaking patented technology consumes 100 times less energy than currently available ultra-low-power processors, all while being programmable with high-level programming languages and AI/ML frameworks. This exceptional efficiency allows for continuous AI/ML operation on a single AA battery for 5-10 years. Our platform's unique capabilities empower IoT devices to intelligently gather and manage first-party data, paving the way for the next computing revolution.We invite skilled and passionate professionals to join us as a Lead Digital Verification Engineer. In this pivotal role, you will spearhead the functional verification of complex SoC/IP designs from specification to tapeout within our newly established hardware engineering team. You will be responsible for defining verification strategies, establishing methodology standards, building and mentoring a team of verification engineers, and ensuring quality and readiness for sign-off. This position requires a robust understanding of modern verification methodologies (UVM, embedded C, and compiler-generated trace-driven testing) and exceptional leadership skills to drive success across multi-block chip programs on schedule. Your contributions will be crucial in refining our internal processes for creating reliable and verified designs, including our upcoming product line that aims to enhance computing performance while optimizing energy efficiency.This is a rare opportunity to influence our development processes and products as we transition from initial development stages to market launch and large-scale production. Join us and help shape the future of computing at the edge and beyond!

Efficient is at the forefront of innovation, developing the world's most energy-efficient general-purpose computer processor. Our patented technology utilizes 100 times less energy than current leading ultra-low-power processors, all while being fully programmable with standard high-level programming languages and AI/ML frameworks. This exceptional efficiency allows for perpetual and pervasive intelligence, enabling AI/ML to operate continuously on a single AA battery for 5-10 years. Our platform's unprecedented efficiency empowers IoT devices to intelligently capture and curate first-party data, fueling the next major computing revolution.We are seeking a highly experienced Design Verification & Emulation Manager to lead, expand, and enhance our verification and emulation organization, a vital component of our newly established hardware engineering team. This high-impact leadership position is responsible for guaranteeing silicon correctness and system-level readiness across multiple industry-defining product lines. You will define the verification strategy from block-level to full-chip, spearhead emulation-based validation for early software enablement, and cultivate a world-class team of verification and emulation engineers.This position uniquely combines deep technical knowledge with strong leadership and program execution capabilities, making it ideal for an individual who excels at the intersection of architecture, verification methodology, hardware-software integration, and team development. This is a rare opportunity to influence our products and processes as we transition from initial product development to market launch and large-scale production. Join us to help shape the future of computing at the edge and beyond!

About ChipStackChipStack stands at the forefront of innovation in semiconductor design, reshaping how we approach chip development in an era defined by complexity and advanced performance demands, particularly in applications like AI.Our dynamic team, composed of experts from renowned tech giants such as Qualcomm, Nvidia, Google, Meta, and the Allen Institute for AI, thrives on rapid execution and technical excellence. Backed by leading investors like Khosla Ventures, Cerberus, and Clear Ventures, we are already making waves with over 10 pioneering customers, ranging from Fortune 100 corporations to groundbreaking AI silicon startups.Role OverviewAs a Research Scientist / Engineer focused on agentic systems, you will design and develop innovative software capable of planning, executing, utilizing tools, and learning autonomously. Your role will involve integrating large language model (LLM) agent research with engineering solutions that enhance chip design workflows.Key ResponsibilitiesAgent Research & PrototypingArchitect and refine agentic components such as memory, context engineering, tool usage, and multi-agent coordination.Experiment with prompting, fine-tuning, and orchestration to optimize agent performance.Infrastructure DevelopmentDevelop scalable infrastructure for prompt iteration, testing, benchmarking, logging, and evaluation.Support pipelines for fine-tuning, automated evaluation, and model deployment.Collaboration & IntegrationCollaborate with chip designers and ML infrastructure engineers to integrate agentic workflows into chip design processes.Work alongside product teams to tackle fundamental agent challenges such as long-horizon planning and tool integration.Research & MetricsEstablish and assess performance metrics for agent systems.Design goal-oriented agentic workflows to improve task completion efficiency.

About Archer Aviation Archer Aviation designs and builds all-electric vertical takeoff and landing (eVTOL) aircraft in San Jose, California. The company focuses on sustainable air mobility, aiming to move four passengers quietly and with minimal environmental impact. The team values ambitious problem-solving and believes that a diverse, inclusive workplace is essential for innovation and success. Every team member’s perspective contributes to the company’s progress. Role Overview: Integration and Verification Engineer, Turbogenerator This engineer leads the verification of integrated hybrid powertrain systems, with a focus on the turboshaft/turbogenerator powertrain and its related components. Main Responsibilities Direct the verification process for integrated hybrid powertrain systems. Apply systems engineering methods to validate the turboshaft/turbogenerator powertrain, including batteries, motors, and complex mechanical parts. Manage verification activities during both bench testing and aircraft integration, including the start of flight test campaigns. Offer technical input in design reviews, especially regarding testing and operational needs for the turbogenerator. Work closely with suppliers, engineers, and other stakeholders to keep verification activities safe and on schedule. Monitor third-party stakeholders to ensure they meet deadlines and uphold safety standards.

Archer, based in San Jose, California, develops all-electric vertical takeoff and landing aircraft designed for four passengers. The company is dedicated to advancing sustainable air mobility and reducing noise pollution through innovative aerospace solutions. Archer values ambitious goals and supports a diverse, inclusive workplace where every team member is respected. Role overview The Powertrain Platform Verification Engineer ensures the reliability and safety of critical platform software used in Archer’s aircraft. This position focuses on thorough testing and validation in line with industry certification standards, especially DO-178C. Main responsibilities Verify and validate safety-critical platform software components according to DO-178C standards. Design and document detailed test plans, test cases, and procedures based on software requirements. Execute Software-in-the-Loop (SIL) and Hardware-in-the-Loop (HIL) tests to evaluate platform software algorithms and low-level drivers. Identify and track software defects using automated systems, collaborating with embedded developers to analyze root causes and verify fixes. Develop and maintain automated test scripts and frameworks in C/C++ and Python to enhance testing efficiency. Create and execute tests for software fault detection and diagnostic algorithms, covering a range of system faults and anomalies. Take part in software audits and reviews to ensure compliance with DO-178C certification requirements.

Archer Aviation, an innovative aerospace firm headquartered in San Jose, California, is on a mission to revolutionize air travel with our all-electric vertical takeoff and landing aircraft. Our commitment to sustainable air mobility drives us to design, manufacture, and operate an aircraft capable of carrying four passengers while minimizing noise pollution.We are passionate about addressing complex challenges and believe that a diverse workforce enhances our problem-solving capabilities, leading to superior insights and success. We strive to foster an equitable and inclusive workplace that celebrates the unique contributions of every team member.Key Responsibilities:Conduct verification and validation of safety-critical software components for the aircraft battery management system (BMS) in alignment with DO-178C standards.Develop and document detailed test plans, cases, and procedures based on software requirements.Perform Software-in-the-Loop (SIL) and Hardware-in-the-Loop (HIL) testing to validate battery algorithms and drivers.Identify, document, and manage software defects using automated tracking systems; collaborate with development teams to analyze root causes and validate resolutions.Create and uphold automated test scripts and frameworks (C/C++, Python) to optimize testing efficiency and coverage.Design and implement tests for verifying software fault detection and diagnostic algorithms, including insulation breakdown, short circuits, and sensor failures.Analyze sensor data (cell voltages, pack current) and test outcomes to ensure accurate state estimation and protective function performance.Engage in software audits and reviews to ensure compliance with DO-178C certification requirements.

At Archer, we are pioneering the future of sustainable air mobility with our innovative all-electric vertical takeoff and landing aircraft, designed to transport four passengers quietly and efficiently. Headquartered in San Jose, California, we are on a mission to revolutionize urban transportation while minimizing our environmental footprint.We are committed to fostering a diverse and inclusive workplace that empowers every team member. Our belief is that varied perspectives ignite creativity, enhance insights, and drive our collective success. Join us as we work together to achieve remarkable things.What You'll Do:As a Staff BMS Hardware Verification Engineer, you will take the lead in the comprehensive verification and validation of Archer’s cutting-edge Battery Management System (BMS) electronics. Your role will ensure that our hardware, sensing, and control circuits fulfill the rigorous safety, reliability, and certification standards essential for eVTOL aircraft. You will create and implement hardware verification plans, design and automate test environments, conduct environmental and functional assessments, and compile certification evidence demonstrating compliance with FAA and industry standards such as DO-160G, DO-254, and ARP4754A. Your contributions will be vital to the certification and safe operation of our battery systems, which are integral to the next generation of urban air mobility.Lead the verification and validation (V&V) processes for the Battery Management System (BMS) electronics utilized in Archer’s high-voltage battery packs.Create detailed hardware verification plans, test procedures, and traceability matrices that align with system and certification requirements (DO-160G, DO-254, ARP4754A).Establish test methodologies for environmental, functional, and safety verification of BMS printed circuit board assemblies (PCBAs) and associated sensing electronics.Collaborate with systems, design, and certification engineering teams to extract verification requirements from system design documentation and certification plans.Design, construct, and automate hardware test setups, including instrumentation, data acquisition systems, power supplies, CAN interfaces, and fault-injection mechanisms.Execute and document test campaigns at the component, subsystem, and integrated aircraft levels to validate compliance with FAA airworthiness standards.Generate comprehensive test reports and assist with certification deliverables, including compliance matrices and traceability documentation.

About UsAt ChipStack, we are at the forefront of revolutionizing chip design in a tech-driven era. With the complexity of chips skyrocketing due to performance demands from applications like AI, our approach seeks to innovate and redefine traditional methodologies that have remained stagnant for decades.Our dynamic team comprises seasoned experts who have previously contributed to renowned organizations such as Qualcomm, Nvidia, Google, Meta, and the Allen Institute for AI. Supported by distinguished investors like Khosla Ventures, Cerberus, and Clear Ventures, we are proud to serve over 10 pioneering clients, ranging from Fortune 100 companies to avant-garde AI silicon startups.About This RoleJoin our founding team as a Research Intern, where you will play a pivotal role in redefining silicon chip design. Collaborate with distinguished chip designers, machine learning scientists, and top-tier software engineers on innovative challenges that push the boundaries of technology.This internship is not conventional; you will tackle real-world problems, develop solutions, and deliver value to actual customers. While we aim to publish your findings in prestigious conferences at the conclusion of the internship, the primary focus will be on creating impactful products that end-users will truly appreciate. If you are passionate about building and deploying AI technologies in a collaborative environment, this opportunity is for you.Note: This role requires in-person attendance in San Jose or Seattle.About YouYou thrive in a startup atmosphere and appreciate the dynamic environment it offers.You are committed to going above and beyond to ensure a stellar experience for every customer.You possess self-motivation, a sense of urgency, and can work independently.You enjoy tackling challenging problems and are eager to explore new territories.This RoleWe seek a dedicated researcher eager to create tangible products. Ideal candidates will be currently pursuing a Ph.D. or M.S. while engaging with leading research groups at their university. The successful candidate will significantly shape the company's product direction and contribute across various facets of our operations.

About EtchedEtched is pioneering the development of the world's first AI inference system specifically designed for transformer models, achieving over 10x the performance and significantly lower costs and latency compared to traditional methods like B200. With our proprietary ASICs, you can create revolutionary products, such as real-time video generation models and highly sophisticated reasoning agents. Supported by substantial investments from top-tier investors and driven by a team of leading engineers, Etched is transforming the infrastructure for the fastest-growing industry of our time.Job OverviewWe are looking for a talented Substrate IC Package Layout Design Engineer to join our dynamic team. In this role, you will oversee the complete design process of intricate IC substrate packages, catering to high-power consumption and high-speed signaling requirements. The ideal candidate will bring substantial experience in large substrate designs (>50mm), complex power delivery networks, and high-speed signaling solutions (up to and exceeding 50GHz). You will collaborate closely with silicon, signal integrity, power integrity, and system engineering teams to co-design state-of-the-art substrates with OSAT providers, with a strong emphasis on optimizing power delivery through substrate technology.Key ResponsibilitiesLead the design and development of sophisticated IC substrate layouts for high-performance AI processors and accelerators.Design complex multi-layer substrate packages (>50mm) with high pin counts and intricate routing requirements.Ensure robust power delivery designs capable of supporting custom silicon solutions exceeding 700W.Develop high-speed signal routing solutions that facilitate >50GHz signaling while minimizing issues such as loss and crosstalk.Work alongside SI/PI engineers to determine signal integrity and power integrity requirements, implementing effective solutions within the substrate layout.Optimize CoWoS (Chip-on-Wafer-on-Substrate) designs for enhanced thermal and electrical performance.Collaborate with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability.Conduct design validation and verification processes to ensure compliance with specifications.

About UsAt ChipStack, we stand at the forefront of the technological revolution, aiming to transform the design of silicon chips which are pivotal in today's tech-centric landscape. While their complexity has surged due to rising performance requirements from applications such as AI, the methods used for their design have remained stagnant for decades. We are determined to innovate and lead this change.Our team is dynamic, highly skilled, and operates with agility. We are comprised of experts with experience at leading technology companies including Qualcomm, Nvidia, Google, Meta, and the Allen Institute for AI. Supported by premier investors such as Khosla Ventures, Cerberus, and Clear Ventures, we have already partnered with over 10 pioneering clients, ranging from Fortune 100 giants to ground-breaking AI silicon startups.About This RoleThis position offers an exceptional opportunity to join the founding team at ChipStack, where we are redefining the approach to modern silicon chip design. Collaborating with seasoned chip designers, machine learning scientists who have successfully trained large language models (LLMs) at scale, and top-tier infrastructure and software engineers, you will leverage your expertise in ML and data infrastructure to tackle some of the most challenging problems in chip design.About YouYou thrive in a startup environment, drawn by the energy and dynamism it provides. You are committed to delivering outstanding customer experiences, willing to go the extra mile to ensure satisfaction. Self-motivated and driven, you possess a strong sense of urgency and the ability to work independently with minimal guidance. You welcome complex problems and relish the opportunity to explore uncharted territories.This RoleWe seek a skilled and experienced ML Infrastructure Engineer to join our founding team. The ideal candidate will have a solid background in designing and scaling ML infrastructure and training pipelines. Your primary responsibility will be to construct the foundational infrastructure that supports the training, fine-tuning, evaluation, and deployment of LLMs in both cloud and on-premise environments. Your contributions will significantly enhance our product capabilities and accelerate our iteration processes.

We are seeking a dedicated and detail-oriented System Verification Specialist II to join our dynamic team at bcforward. In this role, you will be responsible for developing and executing verification strategies to ensure the quality and reliability of our systems. Your expertise will contribute significantly to our mission of delivering top-notch solutions to our clients.

OverviewAccelerating Chip Development with AI.At ChipStack, we are pioneering the integration of AI co-engineers in chip design and verification, aiming to transform multi-year silicon development cycles into mere months. Our goal is to significantly reduce costs, time, and engineering efforts for leading hardware teams globally.Our team consists of a small, highly skilled group with backgrounds from industry giants like Qualcomm, NVIDIA, Google, Meta, and the Allen Institute for AI. Supported by esteemed investors such as Khosla Ventures, Cerberus, and Clear Ventures, ChipStack has already established partnerships with over 10 clients, including Fortune 100 companies and cutting-edge AI silicon startups.We're just getting started with the ChipStack platform. We are committed to tackling some of the most challenging issues in silicon technology and are actively looking for talent. If you are eager to revolutionize chip manufacturing and lead the commercial strategy, we invite you to explore this opportunity.About the Role: Lead SalesAs the inaugural dedicated Sales leader at ChipStack, you will oversee the complete revenue cycle—from outbound prospecting and technical discovery to negotiation, closing, and expansion. You will collaborate with founders, GTM engineers, and product teams to develop a scalable, founder-quality sales process that converts early traction into substantial growth.This is a vital, low-bureaucracy role tailored for a resourceful closer who is passionate about deep technology and excels at building strong customer relationships.What You'll DoDevelop and maintain a robust pipeline of enterprise and startup semiconductor clients.Execute full-cycle sales: prospecting, product demonstrations with GTM engineers, pilot scoping, negotiation, and contract closure.Create a repeatable sales playbook that includes messaging, qualification criteria, and insights from wins and losses.Collaborate with product and engineering teams to translate market feedback into actionable features and roadmap priorities.Own sales forecasts and KPIs; directly report to the CEO and contribute to shaping revenue strategies.Establish the foundation for future sales hires while exemplifying culture and execution.RequirementsAt least 5 years of experience selling complex, technical B2B or enterprise software (experience in EDA, infrastructure, or AI/ML is a plus).Demonstrated success in exceeding quotas on new logo, high-ACV deals.Ability to articulate deep technical value into tangible business outcomes for executive stakeholders.Comfortable operating in dynamic, ambiguous startup settings.Exceptional written and verbal communication skills.