Senior Digital Design Verification Engineer

About OLIXAt OLIX, we are at the forefront of revolutionizing the semiconductor industry. As AI technology rapidly evolves, the demand for advanced infrastructure grows, creating significant opportunities for innovation. Traditional hardware designs are becoming obsolete, and OLIX is leading the charge with our groundbreaking Optical Tensor Processing Unit (OTPU) that delivers unmatched performance and energy efficiency. Join us in shaping the future of AI hardware.The RoleWe are on the lookout for exceptional Senior/Staff Digital Verification Engineers who possess extensive expertise in CMOS digital design and verification. In this role, you will be responsible for ensuring the functional accuracy of high-speed, real-time data processing silicon—from initial algorithm modeling to verified RTL, sign-off, and silicon bring-up.As part of a dynamic, multidisciplinary team, you will contribute to the creation of innovative OTPUs where the digital, optical, and mixed-signal domains converge. We seek candidates who are passionate about developing high-performance systems that power the next generation of AI technology.Key ResponsibilitiesLead the comprehensive verification of high-throughput digital pipelines that support multi-GSPS input rates and continuous streaming data paths.Design and implement robust verification environments using SystemVerilog/UVM, focusing on constrained-random testing, coverage closure, and regression automation.Establish and execute assertion-based verification strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance.Utilize formal verification methods (property checking, assertions, equivalence checking) to enhance simulation-based verification and expedite bug detection.Model and validate algorithms with MATLAB/Simulink or Python to ensure functional equivalence from algorithmic models to RTL and gate-level sign-off.Assist with FPGA prototyping and silicon bring-up by crafting targeted test cases, debugging strategies, and post-silicon validation plans.Collaborate effectively with digital design, optical hardware, mixed-signal, and software teams to guarantee seamless integration and performance.

wehrtyou is hiring a Design Verification Engineer to help ensure the quality and reliability of new designs. This position is available in Austin, Boulder, Chicago, London, or New York. Role overview This role centers on verifying the functionality of complex hardware or system designs. The Design Verification Engineer works closely with colleagues from different teams to review requirements, identify potential issues, and confirm that products meet high quality standards. What you will do Develop and maintain verification plans for new and existing designs Create and execute test cases to validate product functionality Collaborate with engineering and product teams to address issues and improve processes Location Positions are available in Austin, TX; Boulder, CO; Chicago, IL; London, UK; and New York, NY.

Join our dynamic team at Renesas Electronics as a Senior Staff Design Verification Engineer. In this pivotal role, you will leverage your expertise in design verification to ensure the highest quality of our semiconductor products. You will be responsible for developing and implementing verification strategies, collaborating with cross-functional teams, and driving innovation in our design processes.

Neuralink develops devices that connect directly with the human brain. The company’s technology focuses on restoring movement for people with paralysis, improving vision for those with impairments, and changing how people interact with digital systems. The Brain Interfaces Hardware Department leads the design of chip architecture and silicon systems for neural recording and stimulation. This group works on system-on-chip (SoC) solutions that support high-bandwidth brain-machine interfaces. Team members include engineers committed to advancing neurotechnology. Role overview The Physical Design and Verification Engineer manages the full physical design flow from RTL to GDSII. This includes: Synthesis Placement Clock tree synthesis Detailed routing Optimization Physical signoff verification Locations This position is based in Austin, Texas or Fremont, California.

Renesas Electronics Corporation seeks a Staff Design Verification Engineer based in Austin. This position helps maintain high standards during the design verification process, contributing to technology that appears in a wide range of electronic products. Role overview This role focuses on ensuring quality and reliability by verifying design implementations. The work directly impacts technology used in many electronic devices, supporting Renesas’s reputation for dependable products. Key responsibilities Contribute to the design verification process for electronic technologies Help uphold quality standards throughout verification stages Support the development of products used in diverse electronic applications Location This position is based in Austin.

About Etched Etched builds AI inference systems designed specifically for transformer models. The company’s technology delivers over ten times the performance of traditional solutions, while cutting both cost and latency. Etched’s advanced ASICs enable products that were once out of reach for GPUs, such as real-time video generation and complex reasoning agents. Backed by leading venture capital and a team of experienced engineers, Etched is focused on reshaping the infrastructure for one of the fastest-growing industries. Role Overview The Design Verification Engineer - Internal IP will join the Internal IP DV team in Austin. This role centers on validating custom IP blocks that drive Etched’s products, including systolic arrays, DMA engines, and NoCs. The work ensures these components are ready for silicon and deliver high performance. The position involves close collaboration with architects, RTL designers, and software, firmware, and emulation teams to confirm the integrity and efficiency of the hardware-software stack. What You Will Do Develop and maintain UVM/SystemVerilog testbenches for compute arrays, DMA engines, NoCs, and memory subsystems. Design and execute detailed verification plans covering functional correctness, edge cases, concurrency, and performance tuning. Debug complex datapath and protocol issues in RTL and testbench environments. Work directly with architects and designers to validate functionality and design intent. Partner with software, firmware, and emulation teams to support comprehensive bring-up and debugging. Help build reusable DV infrastructure, coverage models, and improve verification methodologies. Qualifications Expert knowledge of UVM and SystemVerilog. Strong analytical and debugging skills for complex digital designs. Solid understanding of computer architecture and core digital design concepts. Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics. Preferred Additional background with verification tools and methodologies is beneficial.

At Tenstorrent, we are at the forefront of AI technology, transforming performance benchmarks, usability, and cost-effectiveness in the industry. As AI reshapes the computing landscape, our solutions are designed to integrate innovations across software models, compilers, platforms, networking, and semiconductors. With a passionate team of technologists, we have engineered a high-performance RISC-V CPU from the ground up, driven by our enthusiasm for AI and our commitment to creating the premier AI platform. We prioritize collaboration, curiosity, and a relentless pursuit of challenging problems. Join us as we expand our team and welcome contributors of all experience levels.We are currently on the lookout for a SoC Physical Design Verification Engineer who will take charge of full-chip signoff and guarantee the manufacturability and high quality of silicon across advanced technology nodes. In this role, you'll spearhead physical verification closures (DRC, LVS, ERC, etc.), troubleshoot issues using standard industry PV tools, and work alongside RTL, PD, CAD, and packaging teams to ensure successful tapeouts. If you thrive in a dynamic environment and relish tackling intricate challenges in cutting-edge silicon, we want to hear from you.This position is hybrid, based in Santa Clara, CA; Austin, TX; or Fort Collins, CO.We invite applicants of various experience levels for this role. During the interview process, we will assess candidates for the appropriate level, and offers will be made accordingly, which may differ from the one in this posting.

About Etched Etched builds the first AI inference system tailored for transformers, delivering more than 10 times the performance of a B200 while cutting costs and latency. The company’s ASIC technology supports products that outpace traditional GPUs, making real-time video generation and advanced reasoning possible. Backed by hundreds of millions in funding and a team of experienced engineers, Etched is reshaping the infrastructure behind today’s fastest-growing industry. Role Overview The Design Verification Engineer - Interface IP will join the Interface IP DV team in Austin. This position works closely with architects, designers, and external vendors to ensure architectural requirements are met when developing IP subsystems and interfaces. The role involves validating correctness and performance across the hardware-software stack, requiring technical skill, creativity, and persistence to solve complex verification problems. What You Will Do Own one or more IP subsystems, such as PCIe, Ethernet, CPU (ARC/ARM), low power peripherals, and sensors. Interpret vendor IP configurations and coordinate with the internal IP team. Build and maintain verification environments using UVM and SystemVerilog to check functional correctness, performance, and compliance with IP specifications. Work with integration and SoC DV teams to ensure external IPs interact smoothly within the overall chip design. Drive coverage closure and sign-off by setting metrics, spotting gaps, and verifying edge cases and stress scenarios thoroughly.

About OLIXAt OLIX, we recognize that the demand for AI technology is accelerating at an unprecedented pace, leading to a significant infrastructure challenge. Current chip and power generation methods are insufficient to meet this demand. The industry is still reliant on outdated hardware designs, which are no longer effective. A transformative approach that enhances speed and efficiency represents the largest economic opportunity of the coming century. OLIX is pioneering this new paradigm with our Optical Tensor Processing Unit (OTPU), which delivers unmatched performance and energy efficiency that existing chips simply cannot achieve.Your RoleWe are in search of exceptional Senior/Staff Digital Design Engineers who specialize in CMOS digital design. You will take complete ownership of the design and implementation of high-speed, real-time data-processing silicon, from initial algorithm modeling through to verified RTL and silicon integration. Join a multidisciplinary team that is at the forefront of developing next-generation OTPUs, where digital, optical, and mixed-signal technologies converge. The ideal candidate will possess a robust background in electrical engineering and semiconductor physics, coupled with a fervor for creating reliable, high-performance digital circuits that propel AI hardware advancements.Key ResponsibilitiesArchitect, design, and implement high-throughput digital pipelines (multi-GSPS input rates, continuous streaming data paths, deep pipelining, and hand-shaking) utilizing advanced CMOS nodes.Quickly prototype and iterate in FPGA (Xilinx/AMD, Intel, or equivalents): develop real-time demonstrations, validate high-speed transceivers, and integrate feedback into ASIC designs.Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence up to gate-level sign-off.Lead RTL development (SystemVerilog / Verilog / VHDL), encompassing synthesis, static-timing closure, and both formal and constrained-random verification.Evaluate power, performance, and area (PPA), employing innovative strategies to meet aggressive bandwidth-per-watt objectives.Collaborate with optical hardware, mixed-signal, and software teams to optimize data-converter interfaces, clock-domain crossings, and firmware abstractions.Mentor junior engineers, facilitate design reviews, and promote best-practice design methodologies.Qualifications & Experience7+ years of direct experience in digital design for high-performance applications.Strong proficiency in CMOS design methodologies and digital circuit development.Extensive experience with FPGA prototyping and algorithm validation.Expertise in RTL design languages (SystemVerilog / Verilog / VHDL) and verification processes.Familiarity with power, performance, and area trade-offs in digital design.Excellent collaborative and communication skills for cross-functional teamwork.Demonstrated ability to lead and mentor engineering teams.

About Neuralink:At Neuralink, we are pioneering the development of innovative devices that facilitate a bi-directional interface with the human brain. Our mission is to restore movement to those affected by paralysis, enable sight for the visually impaired, and transform the way individuals engage with their digital environments.Team Overview:The Brain Interfaces Hardware Department is at the forefront of delivering cutting-edge chip architecture and silicon implementation for neural recording and stimulation system-on-chip (SoC) solutions, aimed at high-bandwidth brain-machine interface applications. Our team consists of highly skilled engineers dedicated to expanding the boundaries of current technology and shaping the future.Role & Responsibilities:As a Digital IC Design Engineer, you will be tasked with the micro-architecture design and register-transfer level (RTL) implementation of digital intellectual properties (IPs) and systems, focusing on high-throughput, low-power digital signal processors (DSPs) and general-purpose hardware accelerators. Ideal candidates will possess product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC.Micro-architecture design and RTL implementation of:Low-power digital signal processorsLow-power general-purpose hardware acceleratorsLow-power graphics processing unitsLow-power radio MAC/PHYLow-power serial link MAC/PHYCollaborate with firmware engineers to design and optimize hardware/software interfaces.Optimize application-specific architectures, including:Complex system modeling for energy and performance benchmarksWorkload analysis and modelingEnergy/performance profiling and analysisTrade-offs between architecture design, process technology, and workload typesBalancing cost and performance amidst manufacturing process variationsEngage in silicon bring-up tests with verification engineers.

Location: Austin, TX (Hybrid: 2 to 3 days onsite per week) Role overview The Senior Staff Systems Design Engineer at Weedmaps leads the transformation of the company’s design system into a scalable, production-ready foundation. This position connects Design, Engineering, and AI tooling, focusing on building, operationalizing, and scaling the system for all user interface surfaces. The role balances rapid development with high standards for usability and craftsmanship, ensuring alignment with engineering architecture and consistency across applications. Collaboration is central, working with Engineering (CI/CD, tokens, tooling), Creative (brand cohesion and evolution), and Product Design (development and iteration) to drive adoption and improve the product experience. What you will do Define and iterate on a multi-platform system for web and mobile, grounded in solid architecture, governance, and scalability principles. Own the system roadmap, setting priorities based on product needs, adoption gaps, and system performance. Collaborate with Design and Creative leaders to ensure quality craftsmanship, modern interaction patterns, and alignment with evolving brand standards. Design and implement core system components, including intuitive, flexible, and scalable APIs, variants, and composition patterns. Maintain high standards for visual accuracy, fidelity, accessibility (using React Aria), and interaction quality, including motion and state management. Continuously improve components based on real product usage and edge case scenarios. Implement automated quality systems such as visual regression testing, and conduct ongoing audits to uphold usability and craftsmanship, taking a cross-functional approach to quality. Lead migration of legacy user interfaces, ensuring smooth integration of key product surfaces (like CTAs and checkout flows) powered by the design system to increase adoption across the platform. Enhance Developer Experience by creating well-structured, intuitive component APIs that balance flexibility and simplicity. Establish a reliable tool-to-code pipeline (Figma, Claude, Builder, and others) to keep design artifacts and production components in sync and minimize drift. Partner with Engineering on architectural decisions (CI/CD, token systems, distribution infrastructure) and support enforcement mechanisms such as linting and token constraints to maintain system integrity. Introduce and standardize AI-assisted workflows, structure components for AI-friendly generation, and integrate tools (Builder.io, Gemini, and others) to improve consistency. Mentor designers and engineers, sharing best practices and guiding system usage to foster a strong, knowledgeable community.

We are seeking a talented and experienced Senior or Principal Engineer in Electronic Design to join our innovative team at dstaff. In this role, you will leverage your expertise in electronic design to contribute to exciting projects that shape the future of technology.Your responsibilities will include leading design efforts, collaborating with cross-functional teams, and ensuring the highest quality standards in electronic components and systems.

Synthesia builds AI video technology for businesses, supporting over 90% of the Fortune 100. Founded in 2017 and based in London, the company operates across Europe and the US, focusing on new ways organizations use video for communication and training. With more than $530 million raised, including a recent $200 million Series E, Synthesia is valued at $4 billion and backed by investors like Accel, NVentures, Kleiner Perkins, GV, Evantic Capital, and founders from Stripe, Datadog, Miro, and Webflow. As AI changes how people interact at work, Synthesia aims to make video content creation straightforward and accessible, helping professionals stay essential within their organizations. Role overview This mid-level digital designer position sits within the Customer Services Content Creation Team in Austin. The team develops tools that let major corporations create video content directly in their browsers. The role centers on designing corporate templates and building visual narratives that help users produce engaging video content without traditional recording equipment. Success in this position requires a proactive mindset, attention to detail, and a drive for high-quality results. What you will do Manage projects from initial concept through to delivery. Present ideas clearly using both verbal and visual communication with internal teams. Design visually impactful work while maintaining consistent brand identity for various organizations. Work collaboratively, contribute ideas, and incorporate feedback throughout the process. Monitor industry trends and bring new concepts into your design projects. Requirements At least 4 years of design experience, with a portfolio demonstrating strong work. Creative approach and ability to handle multiple tasks at once. Interest in motion graphics, branding, and typography. Proficiency with design tools including Figma, Photoshop, and Illustrator.

Join our innovative team at Renesas Electronics as a Senior Staff Design Architecture Engineer. In this pivotal role, you will leverage your extensive expertise to drive the development of advanced design architectures that meet the evolving needs of our customers. Collaborate with cross-functional teams to design, implement, and optimize complex systems that enhance performance and efficiency.

Tenstorrent builds advanced AI hardware and software, with a focus on high-performance RISC-V CPUs. The team brings together specialists in software, compilers, platforms, networking, and semiconductors to tackle complex technical challenges. Collaboration and curiosity shape the company’s approach to product development. Role overview The Staff Engineer, CPU Core Verification leads verification at the CPU core level. This position plays a key part in defining the behavior of out-of-order RISC-V CPUs as they move from design to silicon. Location and work arrangement This is a hybrid role based in Austin, Texas. There is also an option to work from the Santa Clara, California office. Hiring process and leveling Tenstorrent reviews applicants with a range of backgrounds. During interviews, the team evaluates each candidate for the most suitable level. Final compensation aligns with the assessed level, which may differ from the one listed in this posting.

Join Stanley Consultants, an esteemed global consulting engineering firm recognized for its commitment to culture, ethics, and client satisfaction. We tackle complex challenges to foster a sustainable and interconnected world while adapting to technological advancements and resilient practices.With over a century of experience across energy, federal government, transportation, and water sectors, we are shaping the infrastructure that enhances lives. As an employee-owned organization, we prioritize a "People First" approach, valuing your voice, growth, and success.We provide flexible work arrangements, competitive compensation, comprehensive benefits, and the opportunity to build a fulfilling, long-term career.

Join our dynamic Robotics Software Team at avride! We are seeking a skilled Verification & Test Engineer to assist in the development and testing of cutting-edge sensor and system software. This is a part-time, onsite position based at our Austin, TX office, requiring a commitment of 20 hours per week over a 6-month contract.

LPA Design Studios is on the lookout for a seasoned and collaborative Senior Developer to bolster the growth of our Digital Product team within the Inspire Design (ID) division, our integrated technology organization. This role is perfect for a technically adept individual contributor who is enthusiastic about creating scalable digital products that enhance the collaborative efforts of architects, engineers, interior designers, landscape architects, and master planners.In this firmwide role, you will be pivotal in designing, developing, and refining digital products that transform the way LPA plans, designs, delivers, and manages projects. Your contributions will help foster innovative, sustainable projects that offer lasting environmental, economic, and social benefits.Role OverviewInspire Design serves as LPA's integrated technology team, which includes Design Technology (DT), Systems Technology (ST), Data and AI Technology (D+AI), Business Technology (BT), and Digital Product Development (Product).As a vital member of the Digital Product team, the Senior Developer will actively contribute to the delivery of high-quality, user-centric digital solutions. You will collaborate closely with the Digital Manager, product managers, designers, business stakeholders, and other technology groups to translate complex requirements into intuitive, dependable, and scalable solutions.This role emphasizes strong technical execution, teamwork, and mentorship, while adhering to established development standards and best practices.

About Etched Etched builds the first AI inference system tailored for transformers, delivering over 10x higher performance with lower cost and latency than conventional approaches. The company’s ASIC technology powers advanced products, from real-time video generation to sophisticated reasoning agents. Backed by leading investors and staffed by top engineers, Etched is focused on reshaping the infrastructure that supports the fast-moving AI sector. Role Overview The Senior Physical Design Engineer will play a central role in block-level implementation and verification. This position focuses on driving timing closure and optimizing power, performance, and area (PPA). The engineer will oversee third-party design partners and help refine internal workflows to accelerate design cycles. What You Will Do Develop a deep understanding of physical design challenges and solutions Run physical design flows to achieve block closure, improve ASIC infrastructure, and automate design steps Work closely with RTL designers, offering feedback to improve PPA Create dashboards to monitor project convergence in physical design Refine tool flows and collaborate with EDA vendors to adopt new technologies Take responsibility for achieving block-level closure Manage relationships with third-party physical design service providers Who We’re Looking For 5 to 10+ years of hands-on experience in physical design Strong background in tools, flows, and methodologies from RTL synthesis through GDSII sign-off Proven track record in back-end design and timing closure on advanced nodes (5nm and below) Familiarity with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows Experience using sign-off tools such as PrimeTime, Tempus, Voltus, and similar Knowledge of UPF-based low power design, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis Creative thinker with strong problem-solving skills Location Austin

About Neuralink:At Neuralink, we are pioneering technology that establishes a bi-directional interface with the human brain. Our innovative devices aim to restore movement to those who are paralyzed, restore sight to the visually impaired, and transform the way humans engage with their digital environments.Team Overview:The EPC team plays a crucial role in all engineering, procurement, and construction activities, from developing new greenfield sites to enhancing existing facilities. We collaborate with cross-functional teams to identify and address their present and future requirements, creating tailored environments that foster the growth of our research and engineering initiatives.We seek dynamic individuals who thrive in fast-paced settings, advocate for teamwork and transparent communication, and possess a genuine enthusiasm for design and construction. This role demands exceptional organizational skills, a consistent track record of high-performance, a passion for interdisciplinary projects, and an eagerness to contribute to Neuralink's mission!Key Responsibilities:As a senior mechanical engineer on our design team, you will be instrumental in conceptualizing and optimizing facilities. You will translate innovative concepts into detailed designs for HVAC, hydronic (chilled and heating water), plumbing, and process utility systems that seamlessly integrate with our facilities and manufacturing processes. Your work will encompass new construction as well as modifications to existing infrastructures. This position will support construction, facility operations, and various cross-functional departments to ensure that infrastructure systems are expertly designed to support all company activities.Develop conceptual designs and finalize designs for diverse project types including offices, laboratories, clean rooms, manufacturing facilities, warehouses, data centers, vivariums, and animal care facilities.Create high-quality Building Information Modeling (BIM) (REVIT) models, engineering drawings, and one-line diagrams for all mechanical, plumbing, and process systems.Design HVAC, hydronic, plumbing, and process utility systems that comply with codes, remain cost-effective, and satisfy quality and scheduling requirements.Prepare comprehensive construction drawing packages, including details, specifications, and operational sequences.Generate Building Automation System (BAS) and Direct Digital Control (DDC) control documents, scopes of work, and vendor quotes.Develop specifications, data sheets, and procurement requests for proposals (RFPs) for long-lead mechanical and plumbing equipment.Ensure all designs adhere to relevant codes and standards for optimal performance.