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Design Verification Engineer - Internal IP

EtchedAustin
On-site Full-time

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Experience Level

Experience

Qualifications

Ideal Candidate QualificationsExpertise in UVM and SystemVerilog. Strong analytical skills and ability to debug complex digital designs. Deep understanding of computer architecture and foundational digital design principles. Practical experience in verifying datapaths, memory systems, interconnects, or high-throughput fabrics.

About the job

About Etched

Etched builds AI inference systems designed specifically for transformer models. The company’s technology delivers over ten times the performance of traditional solutions, while cutting both cost and latency. Etched’s advanced ASICs enable products that were once out of reach for GPUs, such as real-time video generation and complex reasoning agents. Backed by leading venture capital and a team of experienced engineers, Etched is focused on reshaping the infrastructure for one of the fastest-growing industries.

Role Overview

The Design Verification Engineer - Internal IP will join the Internal IP DV team in Austin. This role centers on validating custom IP blocks that drive Etched’s products, including systolic arrays, DMA engines, and NoCs. The work ensures these components are ready for silicon and deliver high performance. The position involves close collaboration with architects, RTL designers, and software, firmware, and emulation teams to confirm the integrity and efficiency of the hardware-software stack.

What You Will Do

  • Develop and maintain UVM/SystemVerilog testbenches for compute arrays, DMA engines, NoCs, and memory subsystems.
  • Design and execute detailed verification plans covering functional correctness, edge cases, concurrency, and performance tuning.
  • Debug complex datapath and protocol issues in RTL and testbench environments.
  • Work directly with architects and designers to validate functionality and design intent.
  • Partner with software, firmware, and emulation teams to support comprehensive bring-up and debugging.
  • Help build reusable DV infrastructure, coverage models, and improve verification methodologies.

Qualifications

  • Expert knowledge of UVM and SystemVerilog.
  • Strong analytical and debugging skills for complex digital designs.
  • Solid understanding of computer architecture and core digital design concepts.
  • Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.

Preferred

  • Additional background with verification tools and methodologies is beneficial.

About Etched

At Etched, we are pioneering the development of the world's first AI inference system specifically designed for transformers. Our innovative technology offers over 10 times the performance of traditional systems while significantly reducing cost and latency. With our advanced ASICs, you will be able to create products that were once thought impossible with GPUs, such as real-time video generation and highly complex reasoning agents. Supported by substantial investments from leading venture capitalists and driven by a team of top engineers, Etched is at the forefront of transforming the infrastructure for the fastest-growing industry in history.

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