CAD Hardware-Software Infrastructure Engineer

At Archer, we are pioneering the future of sustainable air mobility with our innovative all-electric vertical takeoff and landing aircraft, designed to transport four passengers quietly and efficiently. Headquartered in San Jose, California, we are on a mission to revolutionize urban transportation while minimizing our environmental footprint.We are committed to fostering a diverse and inclusive workplace that empowers every team member. Our belief is that varied perspectives ignite creativity, enhance insights, and drive our collective success. Join us as we work together to achieve remarkable things.What You'll Do:As a Staff BMS Hardware Verification Engineer, you will take the lead in the comprehensive verification and validation of Archer’s cutting-edge Battery Management System (BMS) electronics. Your role will ensure that our hardware, sensing, and control circuits fulfill the rigorous safety, reliability, and certification standards essential for eVTOL aircraft. You will create and implement hardware verification plans, design and automate test environments, conduct environmental and functional assessments, and compile certification evidence demonstrating compliance with FAA and industry standards such as DO-160G, DO-254, and ARP4754A. Your contributions will be vital to the certification and safe operation of our battery systems, which are integral to the next generation of urban air mobility.Lead the verification and validation (V&V) processes for the Battery Management System (BMS) electronics utilized in Archer’s high-voltage battery packs.Create detailed hardware verification plans, test procedures, and traceability matrices that align with system and certification requirements (DO-160G, DO-254, ARP4754A).Establish test methodologies for environmental, functional, and safety verification of BMS printed circuit board assemblies (PCBAs) and associated sensing electronics.Collaborate with systems, design, and certification engineering teams to extract verification requirements from system design documentation and certification plans.Design, construct, and automate hardware test setups, including instrumentation, data acquisition systems, power supplies, CAN interfaces, and fault-injection mechanisms.Execute and document test campaigns at the component, subsystem, and integrated aircraft levels to validate compliance with FAA airworthiness standards.Generate comprehensive test reports and assist with certification deliverables, including compliance matrices and traceability documentation.

Archer Aviation is an innovative aerospace company headquartered in San Jose, California, dedicated to revolutionizing air travel with our all-electric vertical takeoff and landing aircraft. Our mission is to enhance the future of sustainable air mobility, providing a quiet and eco-friendly mode of transportation for up to four passengers.At Archer, we are committed to tackling significant challenges with high aspirations. We recognize that a diverse workforce fosters smarter solutions and deeper insights, ultimately guiding us to success. We strive to create an equitable and inclusive workplace that honors our differences and supports every team member.Key Responsibilities:As the BMS Hardware Manager, you will spearhead the development of Archer's high voltage battery management system (BMS) and charge control unit (CCU).Your specific duties will include:Building and mentoring a team of electrical engineers focused on BMS and CCU hardware development.Driving architectural decisions and evaluating new hardware concepts to enhance maturity.Making pivotal technical choices while balancing performance, safety, timelines, and certification requirements.Leading engineering design reviews and overseeing flight hardware releases.Guiding cross-functional teams in hardware analysis projects such as WCCA, FMEA, and PSSA to ensure safe flight and certification.Managing technical interactions with suppliers, partners, and regulatory authorities.Supporting Manufacturing, Quality, and Supply Chain teams during new product introduction (NPI) and production ramp-up.Collaborating with program teams to deliver high-quality hardware within established timelines.Coordinating with integration and testing teams during the deployment of hardware across integrated test labs and aircraft.

Archer Aviation is at the forefront of aerospace innovation, based in San Jose, California. We are pioneering the development of an all-electric vertical takeoff and landing aircraft, with a commitment to enhancing sustainable air mobility. Our aircraft design focuses on transporting four passengers while minimizing noise pollution.We aim high and tackle challenging problems, believing that workplace diversity fuels our intelligence, enhances insights, and propels our collective success. Our commitment to fostering an equitable and inclusive environment ensures that we celebrate and support the unique contributions of all team members.Key Responsibilities:As a Senior BMS Hardware Systems Engineer, you will spearhead the development and execution of airborne electronic hardware systems for Archer's high voltage Battery Management System (BMS). Your expertise will ensure compliance with rigorous safety, reliability, and certification standards essential for eVTOL aircraft. You'll be tasked with creating and managing detailed electronic hardware requirements and design documentation, directly influencing the certification and safe operation of Archer's battery systems that power the future of urban air mobility.Collaborate across engineering disciplines to support the implementation of high-reliability, safety-critical systems for aircraft design.Develop comprehensive hardware requirements and traceability matrices aligned with system and certification standards (DO-254, ARP4754A).Define and decompose hardware system requirements, ensuring traceability through the overall system architecture.Create robust system/subsystem interface definitions.Coordinate with regulatory bodies and Designated Engineering Representatives (DERs) during the development and review of AEH certification substantiation artifacts.Work closely with the electrical design team to ensure product alignment with business requirements.Engage in design reviews, hardware qualification, and root cause analysis to guarantee robust and certifiable hardware performance.

At Efficient Computer, we are at the forefront of technological innovation, developing the world's most energy-efficient general-purpose computer processor. Our groundbreaking patented technology consumes 100 times less energy than currently available ultra-low-power processors, all while being programmable with high-level programming languages and AI/ML frameworks. This exceptional efficiency allows for continuous AI/ML operation on a single AA battery for 5-10 years. Our platform's unique capabilities empower IoT devices to intelligently gather and manage first-party data, paving the way for the next computing revolution.We invite skilled and passionate professionals to join us as a Lead Digital Verification Engineer. In this pivotal role, you will spearhead the functional verification of complex SoC/IP designs from specification to tapeout within our newly established hardware engineering team. You will be responsible for defining verification strategies, establishing methodology standards, building and mentoring a team of verification engineers, and ensuring quality and readiness for sign-off. This position requires a robust understanding of modern verification methodologies (UVM, embedded C, and compiler-generated trace-driven testing) and exceptional leadership skills to drive success across multi-block chip programs on schedule. Your contributions will be crucial in refining our internal processes for creating reliable and verified designs, including our upcoming product line that aims to enhance computing performance while optimizing energy efficiency.This is a rare opportunity to influence our development processes and products as we transition from initial development stages to market launch and large-scale production. Join us and help shape the future of computing at the edge and beyond!

Archer Aviation Inc. is a pioneering aerospace company headquartered in San Jose, California, dedicated to developing an all-electric vertical takeoff and landing (eVTOL) aircraft. Our mission is to revolutionize sustainable air mobility, creating a quieter and eco-friendly mode of transportation that can accommodate up to four passengers.At Archer, we strive for excellence and face complex challenges, and we believe that fostering a diverse workplace enhances our creativity and insights, ultimately driving our collective success. We are committed to establishing an equitable and inclusive environment that values our differences and celebrates every team member.What You’ll Do:As a BMS Integration Engineer, you will be responsible for the integration of hardware and software components for Archer's high voltage battery management system (BMS). Your contributions will encompass all stages of the product development lifecycle, including development, implementation, validation, and ongoing enhancements.In this role, you will…Collaborate closely with hardware engineers and software developers to activate new features in the labTransform schematics and datasheets into pseudocode, timing diagrams, and interface specificationsEngage hands-on in the lab to establish equipment and instrumentation as neededDiagnose and resolve cross-functional hardware-software issuesSupport the battery testing team and mechanical teams during critical battery pack evaluations at test locationsCreate automated fault injection tests and fixtures to evaluate safety-critical diagnosticsCompile design feedback to inform improvements for future versions of the BMS hardware

About Archer Aviation Archer Aviation designs and builds all-electric vertical takeoff and landing (eVTOL) aircraft in San Jose, California. The company focuses on sustainable air mobility, aiming to move four passengers quietly and with minimal environmental impact. The team values ambitious problem-solving and believes that a diverse, inclusive workplace is essential for innovation and success. Every team member’s perspective contributes to the company’s progress. Role Overview: Integration and Verification Engineer, Turbogenerator This engineer leads the verification of integrated hybrid powertrain systems, with a focus on the turboshaft/turbogenerator powertrain and its related components. Main Responsibilities Direct the verification process for integrated hybrid powertrain systems. Apply systems engineering methods to validate the turboshaft/turbogenerator powertrain, including batteries, motors, and complex mechanical parts. Manage verification activities during both bench testing and aircraft integration, including the start of flight test campaigns. Offer technical input in design reviews, especially regarding testing and operational needs for the turbogenerator. Work closely with suppliers, engineers, and other stakeholders to keep verification activities safe and on schedule. Monitor third-party stakeholders to ensure they meet deadlines and uphold safety standards.

Archer, based in San Jose, California, develops all-electric vertical takeoff and landing aircraft designed for four passengers. The company is dedicated to advancing sustainable air mobility and reducing noise pollution through innovative aerospace solutions. Archer values ambitious goals and supports a diverse, inclusive workplace where every team member is respected. Role overview The Powertrain Platform Verification Engineer ensures the reliability and safety of critical platform software used in Archer’s aircraft. This position focuses on thorough testing and validation in line with industry certification standards, especially DO-178C. Main responsibilities Verify and validate safety-critical platform software components according to DO-178C standards. Design and document detailed test plans, test cases, and procedures based on software requirements. Execute Software-in-the-Loop (SIL) and Hardware-in-the-Loop (HIL) tests to evaluate platform software algorithms and low-level drivers. Identify and track software defects using automated systems, collaborating with embedded developers to analyze root causes and verify fixes. Develop and maintain automated test scripts and frameworks in C/C++ and Python to enhance testing efficiency. Create and execute tests for software fault detection and diagnostic algorithms, covering a range of system faults and anomalies. Take part in software audits and reviews to ensure compliance with DO-178C certification requirements.

Archer Aviation, an innovative aerospace firm headquartered in San Jose, California, is on a mission to revolutionize air travel with our all-electric vertical takeoff and landing aircraft. Our commitment to sustainable air mobility drives us to design, manufacture, and operate an aircraft capable of carrying four passengers while minimizing noise pollution.We are passionate about addressing complex challenges and believe that a diverse workforce enhances our problem-solving capabilities, leading to superior insights and success. We strive to foster an equitable and inclusive workplace that celebrates the unique contributions of every team member.Key Responsibilities:Conduct verification and validation of safety-critical software components for the aircraft battery management system (BMS) in alignment with DO-178C standards.Develop and document detailed test plans, cases, and procedures based on software requirements.Perform Software-in-the-Loop (SIL) and Hardware-in-the-Loop (HIL) testing to validate battery algorithms and drivers.Identify, document, and manage software defects using automated tracking systems; collaborate with development teams to analyze root causes and validate resolutions.Create and uphold automated test scripts and frameworks (C/C++, Python) to optimize testing efficiency and coverage.Design and implement tests for verifying software fault detection and diagnostic algorithms, including insulation breakdown, short circuits, and sensor failures.Analyze sensor data (cell voltages, pack current) and test outcomes to ensure accurate state estimation and protective function performance.Engage in software audits and reviews to ensure compliance with DO-178C certification requirements.

Join Our Team at EtchedAt Etched, we are pioneering the development of the first AI inference system specifically designed for transformers, achieving over 10x the performance and significantly lower costs and latency compared to traditional solutions like the B200. Our custom ASICs empower the creation of groundbreaking products, such as real-time video generation models and highly advanced reasoning agents. Backed by substantial investments from leading venture capitalists and a team of top engineers, we are reshaping the foundational technology of one of the fastest-growing industries in history.Role OverviewWe are looking for a talented Design Verification Engineer to become a vital part of our Systems/Performance Verification team. In this role, you will be responsible for ensuring that the custom IPs driving our innovative Sohu architecture—such as systolic arrays, DMA engines, and Network on Chip (NoC)—are reliable, high-performing, and ready for silicon implementation. This position requires innovative thinking, robust technical skills, and a passion for solving intricate verification challenges. You will collaborate closely with architects, RTL designers, and software/firmware/emulation teams to validate the accuracy and performance of our hardware-software integration.Key ResponsibilitiesCollaborate with architects and RTL designers to verify the performance features of the design and ensure alignment with performance models, both pre- and post-silicon.Partner with software and application developers to identify performance bottlenecks and optimize software solutions.Create comprehensive test plans and develop test infrastructure/tools aimed at performance tuning, correlation, and verification.Enhance and maintain architectural performance models.Design tests in SystemVerilog, Python, or other vectors to debug and correlate RTL with performance models.Develop SystemVerilog or Python-based checkers to validate performance features.Implement coverage monitors and perform coverage analysis to ensure comprehensive testing of all performance features.Investigate performance issues and execute performance tuning on silicon.Lead end-to-end performance tuning to guarantee optimal hardware utilization, software efficiency, and architectural coherence throughout the ASIC design lifecycle.

Join our innovative team at Etched as an Electrical Engineer specializing in Hardware Systems. In this role, you'll be responsible for designing, developing, and testing cutting-edge hardware solutions that meet the evolving needs of our clients. You will collaborate with cross-functional teams to ensure the successful implementation of advanced technologies.Your expertise will contribute to the creation of high-quality electronic systems, ensuring they are reliable and efficient. We are looking for a proactive engineer who thrives in a fast-paced environment and is passionate about technology and innovation.

About UsAt chipstack, we are revolutionizing the way chips are designed in an era where the complexity and demands of technology are constantly evolving. Our team combines expertise from top-tier companies such as Qualcomm, Nvidia, Google, and Meta, and we are passionate about integrating artificial intelligence into the Electronic Design Automation (EDA) landscape.Backed by leading investors like Khosla Ventures and Cerberus, we are already working with over 10 pioneering customers, ranging from Fortune 100 companies to innovative AI silicon startups. Join us as we drive the future of chip design.Position OverviewWe are on the lookout for a motivated Functional Verification Engineer with a strong background in UVM test bench development. Your role will be pivotal in harnessing AI to transform traditional verification methodologies, ensuring the design and validation of cutting-edge semiconductor technologies. Collaborating with a talented team of machine learning and software engineers, you will utilize advanced AI tools to innovate our verification processes.Key Responsibilities• Drive the application of machine learning to enhance pre-silicon functional verification methodologies including UVM.• Utilize AI-powered EDA tools to streamline design and verification workflows.• Identify challenges within UVM verification and implement AI-driven solutions.• Collaborate with customers to understand their needs and provide groundbreaking verification strategies.• Work closely with machine learning and software engineering teams to ensure high-quality outputs.• Stay updated on the latest advancements in AI-powered hardware verification and contribute to internal knowledge sharing.Required Qualifications• Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.• A minimum of 3 years of experience in digital design and verification, with a strong emphasis on UVM.

About Etched Etched builds the first AI inference system tailored for transformers. The company’s custom ASICs deliver over 10x the performance of standard solutions, with lower costs and latency than a B200. These chips enable products like real-time video generation models and advanced reasoning agents. Etched is backed by major investors and staffed by engineers focused on reshaping AI infrastructure. Role Overview: Design Verification Engineer - SoC This San Jose-based role sits within the Systems and Performance Verification team. The Design Verification Engineer ensures Etched’s custom IPs, including systolic arrays, DMA engines, and NoCs, are ready for silicon. The work spans verifying performance, collaborating with architects and designers, and supporting the entire hardware-software stack. Expect to tackle complex verification challenges alongside colleagues in architecture, RTL, and software/firmware. What You Will Do Work with architects and RTL designers to verify performance features against models, both before and after silicon. Collaborate with software teams to spot and resolve performance bottlenecks. Create test plans and develop tools for performance tuning, correlation, and verification. Maintain and improve architectural performance models. Write tests in SystemVerilog, Python, or vectors to debug and align RTL with performance models. Develop checkers in SystemVerilog or Python to verify performance features. Implement coverage monitors and analyze results to ensure thorough testing. Investigate and tune performance issues on silicon. Lead end-to-end performance tuning to optimize hardware use, software efficiency, and architectural fit across the ASIC design lifecycle. What Makes a Strong Candidate Understanding of digital design, RTL, and ASIC design flows. Hands-on experience with performance verification tools and methodologies. Strong analytical and problem-solving abilities. Comfort working on several projects at once and adapting to shifting priorities.

About EtchedEtched is at the forefront of innovation, developing the world’s first AI inference system specifically designed for transformers. Our technology outperforms traditional GPUs with over 10x greater performance, significantly reducing cost and latency compared to existing solutions. With Etched ASICs, we're enabling the creation of groundbreaking products, such as real-time video generation models and highly complex reasoning agents. Our team, comprised of top engineers, is supported by substantial investments from leading investors, and we are redefining the infrastructure for the rapidly evolving AI industry.Job SummaryWe are looking for a passionate Design Verification Engineer to join our Internal IP DV team. In this role, you will be responsible for ensuring that the custom IPs that drive Sohu—such as systolic arrays, DMA engines, and NoCs—are robust, high-performance, and ready for silicon implementation. This position requires both creativity and deep technical expertise to address complex verification challenges. You will work in collaboration with architects, RTL designers, and software/firmware/emulation teams to validate correctness and performance across the entire hardware-software stack.Key ResponsibilitiesDesign, develop, and maintain UVM/SystemVerilog testbenches for high-performance IPs including compute arrays, DMAs, NoCs, and memory subsystems.Create and implement comprehensive verification plans that address functional correctness, corner cases, concurrency issues, and performance bottlenecks.Troubleshoot complex datapath and protocol issues within RTL and testbench environments.Collaborate closely with architects and designers to confirm functionality and design intent.Engage with software, firmware, and emulation teams to ensure thorough end-to-end bring-up and debugging coverage.Contribute to the development of reusable DV infrastructure, coverage models, and improvements in methodology.QualificationsYou may be an ideal candidate if you possess the following qualifications:Expertise in UVM and SystemVerilog.Exceptional debugging and problem-solving skills related to complex digital designs.In-depth knowledge of computer architecture and the fundamentals of digital design.Hands-on experience in verifying datapaths, memory systems, interconnects, or high-throughput fabrics.

About EtchedEtched is pioneering the world’s first AI inference system specifically designed for transformers, achieving over 10 times greater performance and significantly reduced costs and latency compared to traditional solutions like B200. Our ASICs enable the development of products that were previously unattainable with GPUs, including real-time video generation models and highly advanced parallel reasoning agents. With substantial backing from leading investors and a team of exceptional engineers, Etched is transforming the infrastructure landscape for one of the fastest-growing industries.Job SummaryWe are on the lookout for a talented Design Verification Engineer to join our Interface IP DV team. In this role, you will collaborate with architects, designers, and vendors to ensure that all architectural requirements are flawlessly integrated into the IP subsystems and interfaces we are developing. You will validate the correctness and performance across the entire hardware-software stack. This position requires creativity, strong technical skills, and a passion for overcoming complex verification challenges.Key ResponsibilitiesTake complete ownership of one or more IP subsystems, including PCIe, Ethernet, CPU (ARC/ARM), low-power peripherals, and sensors.Comprehend vendor IP configurations and facilitate communication with the internal IP team.Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.Collaborate with integration and SoC DV teams to ensure the seamless operation of external IPs within the overall chip architecture.Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring thorough verification across corner cases and stress scenarios.

At Efficient, we are revolutionizing the computing landscape with our cutting-edge, energy-efficient general-purpose processor. Our groundbreaking technology consumes 100 times less energy than the leading ultra-low-power processors available today, while remaining compatible with standard high-level programming languages and AI/ML frameworks. This exceptional efficiency allows for continuous AI/ML operation on a single AA battery for 5 to 10 years, making it easier than ever to harness the power of IoT devices for capturing and curating first-party data that will drive the next computing revolution.We are on the lookout for a CAD Lead - Physical Design Flows and Infrastructure to join our innovative hardware engineering team. This unique opportunity allows you to establish CAD flows and infrastructure from the ground up, shaping the future of our physical design methodologies.As a pivotal member of our newly formed hardware engineering group, you will play a critical role in transitioning our products from initial development stages to market launch and high-volume production. Join us in redefining the future of edge computing!Key ResponsibilitiesDevelop and drive physical design flows and methodologies for advanced FinFET and multi-patterning technologies using Cadence Tempus or Synopsys Primetime.Create repeatable, predictable design processes that are agnostic to specific designs and methodologies.Build infrastructure that enables consistent, rapid design under tight timelines for a diverse range of product lines in the energy-efficient edge AI computing sector.Collaborate closely with physical design team leads to establish comprehensive build and signoff flows.Develop regression frameworks to ensure high-quality flows, allowing engineers to devote over 90% of their time to design tasks rather than tool management.Create quality-checking utilities to enhance design efficiency.Implement a unified environment for managing all collateral specifications (standard cells, memory, PDK, hard IPs) and flow dependencies (cycle time, PVTRC corners, design configurations).Coordinate with third-party vendor resources to optimize workflow.Pursue continuous improvements in flow consistency and efficiency across multiple product lines.

Efficient Computer is pioneering the development of the world’s most energy-efficient general-purpose computer processor. Our patented technology utilizes 100 times less energy than the leading commercially available ultra-low-power processors, while being programmable through standard high-level programming languages and AI/ML frameworks. This groundbreaking efficiency enables the possibility of perpetual, pervasive intelligence, allowing AI/ML to operate continuously on a single AA battery for 5-10 years. Our platform's unprecedented energy efficiency empowers IoT devices to intelligently capture and curate first-party data, driving the next major computing revolution.We are looking for a Lead Physical Design Engineer to join our newly established hardware engineering organization. The successful candidate will spearhead the physical design convergence of IPs and complete SOC. You will provide technical leadership from a physical design perspective and will play a key role in hiring and mentoring the PD team to unify all facets of Efficient's processor designs. This position involves hands-on responsibilities, including driving the PNR methodology (Floorplanning, Placement, Clock Tree Design, Routing, and Low Power Design). We adhere to a correct-by-construction philosophy and prioritize the accuracy of PNR flows in relation to signoff considerations. The PD lead will ensure that methodologies are established to balance timing and power tradeoffs, optimizing both aspects effectively. This role is cross-functional, working within a highly integrated team of world-class engineers focused on an energy-efficient processor through integrated hardware/software co-design.This is a unique opportunity to join a hardware engineering organization at its inception and influence our products as we transition from initial stages of product development to market release and scaled volume production. Join us in shaping the future of computing at the edge and beyond!

Astera Labs is looking for an Electrical Hardware Engineering Intern to join the Hardware Design Group in San Jose, CA for 2026. This internship offers practical experience in hardware design and development, working directly with a team focused on connectivity ASICs. Role overview This position centers on supporting the design and development of hardware products. Interns will work closely with experienced engineers, gaining exposure to the full hardware development process. What you will do Assist with hardware design activities for devices that use Astera Labs connectivity ASICs Help with the development and initial bring-up of significant hardware projects Work on key engineering tasks as part of a collaborative team Location This internship is based in San Jose, CA.

Join our dynamic team as a Hardware Lab Technician in San Jose, where you will play a crucial role in supporting hardware development and testing processes. You will work closely with engineers and product teams to ensure that our hardware products meet the highest standards of quality and performance. Your responsibilities will include conducting tests, troubleshooting hardware issues, and documenting results.

About UsAt Chipstack, we recognize that chips are the backbone of modern technology, yet the design processes have not evolved significantly over the decades. The rising complexity and specialization needed to meet performance demands from AI applications drive our mission to innovate the chip design landscape.Our agile and technically adept team is composed of experts with backgrounds in esteemed companies like Qualcomm, Nvidia, Google, Meta, and the Allen Institute for AI. We’re supported by prominent investors such as Khosla Ventures, Cerberus, and Clear Ventures, and we have successfully partnered with over 10 pioneering customers, ranging from Fortune 100 firms to revolutionary AI silicon startups.About This RoleWe are on the lookout for a skilled Formal Verification Engineer to become a vital part of our innovative team. The ideal candidate will possess extensive experience in all areas of Formal Verification, including SVA, Property Verification, Formal Methods/Abstractions, and Methodology, along with scripting proficiency. In this role, you will contribute to the development of Chipstack’s groundbreaking Formal Verification Agent, playing a crucial part in enhancing the quality and capabilities of our tools.You will collaborate closely with seasoned chip designers who have crafted intricate chips, machine learning scientists who have scaled LLM training, and exceptional infrastructure and software engineers. Your expertise in Formal Verification will be instrumental in creating the next generation of AI-integrated verification tools.