About the job
Join Happiest Minds as an ASIC Verification Engineer: 5-8 years of experience required for 2 available positions.
- Independently develop a comprehensive verification environment utilizing advanced verification languages such as System Verilog.
Implement methodologies based on OVM/UVM frameworks to enhance verification processes.
Proficiency with Synopsys VCS and Mentor Questa is essential.
- Analyze and execute existing verification workflows while proactively refining the framework.
- Engage in the development and implementation of verification methodologies.

