About the job
At DiffLogic, we are pioneering advancements in artificial intelligence with a bold objective: to revolutionize matrix multiplication. Instead of merely running models on chips, we create chips that embody the models themselves. For us, tape-out is not just a milestone—it's the product itself. We embrace rapid iteration, frequently tape out, and ensure that each new production yields smarter silicon than its predecessor.
We are seeking outstanding physical design flow engineers to assume complete responsibility for the RTL-to-GDSII pipeline. This includes synthesis, place & route (P&R), power and timing analysis, signoff (DRC/LVS, etc.), and negotiating foundry waivers and handoffs. If you have a track record of successful tape-outs, can effectively close timing independently, and are proficient in Synopsys and Cadence tools, we want to hear from you. Here, you will have the opportunity to ship more silicon in two years than most engineers do in a decade. If you are passionate about fully automated flows and aspire to scale to over 100mm² per month, apply today!

